Commit 585e58f4 authored by Yong Wu's avatar Yong Wu Committed by Will Deacon
Browse files

iommu/mediatek: Add iova_region structure 



Add a new structure for the iova_region. Each a region will be a
independent iommu domain.

For the previous SoC, there is single iova region(0~4G). For the SoC
that need support multi-domains, there will be several regions.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarTomasz Figa <tfiga@chromium.org>
Link: https://lore.kernel.org/r/20210111111914.22211-27-yong.wu@mediatek.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b7875eb9

drivers/iommu/mtk_iommu.c

+19 −0
Original line number Diff line number Diff line
@@ -167,6 +167,15 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 


#define for_each_m4u(data)	list_for_each_entry(data, &m4ulist, list)



struct mtk_iommu_iova_region {

	dma_addr_t		iova_base;

	unsigned long long	size;

};



static const struct mtk_iommu_iova_region single_domain[] = {

	{.iova_base = 0,		.size = SZ_4G},

};



/*

 * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain

 * for the performance.
@@ -901,6 +910,8 @@ static const struct mtk_iommu_plat_data mt2712_data = { 
	.m4u_plat     = M4U_MT2712,

	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.iova_region  = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),

	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},

};
@@ -908,6 +919,8 @@ static const struct mtk_iommu_plat_data mt6779_data = { 
	.m4u_plat      = M4U_MT6779,

	.flags         = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,

	.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,

	.iova_region   = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),

	.larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},

};
@@ -915,6 +928,8 @@ static const struct mtk_iommu_plat_data mt8167_data = { 
	.m4u_plat     = M4U_MT8167,

	.flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.iova_region  = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),

	.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */

};
@@ -923,6 +938,8 @@ static const struct mtk_iommu_plat_data mt8173_data = { 
	.flags	      = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |

			HAS_LEGACY_IVRP_PADDR,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.iova_region  = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),

	.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */

};
@@ -930,6 +947,8 @@ static const struct mtk_iommu_plat_data mt8183_data = { 
	.m4u_plat     = M4U_MT8183,

	.flags        = RESET_AXI,

	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,

	.iova_region  = single_domain,

	.iova_region_nr = ARRAY_SIZE(single_domain),

	.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},

};

drivers/iommu/mtk_iommu.h

+5 −0
Original line number Diff line number Diff line
@@ -45,10 +45,15 @@ enum mtk_iommu_plat { 
	M4U_MT8183,

};



struct mtk_iommu_iova_region;



struct mtk_iommu_plat_data {

	enum mtk_iommu_plat m4u_plat;

	u32                 flags;

	u32                 inv_sel_reg;



	unsigned int				iova_region_nr;

	const struct mtk_iommu_iova_region	*iova_region;

	unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];

};