Commit 582ffae8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset 



Apparently the PCIe capability is at address 0x40 in config space of X-Gene
v1 Root Ports.  Add a definition of that and use the generic PCI_EXP_RTCTL
offset into the capability.  No functional change intended.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent c7aca96a

drivers/pci/host/pci-xgene.c

+2 −2
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ 
#define SZ_1T				(SZ_1G*1024ULL)

#define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)



#define ROOT_CAP_AND_CTRL		0x5C

#define XGENE_V1_PCI_EXP_CAP		0x40



/* PCIe IP version */

#define XGENE_PCIE_IP_VER_UNKN		0
@@ -189,7 +189,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, 
	 * Avoid this by not claiming to support CRS.

	 */

	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&

	    ((where & ~0x3) == ROOT_CAP_AND_CTRL))

	    ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))

		*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);



	if (size <= 2)