Commit 58091b49 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-fixes-2022-08-22' of https://github.com/intel/gvt-linux into drm-intel-fixes 



gvt-fixes-2022-08-22

- CometLake regression fix in mmio table rework (Alex)
- misc kernel doc and typo fixes

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220822031215.GJ1089@zhen-hp.sh.intel.com
parents 1c23f9e6 b75ef35b

drivers/gpu/drm/i915/gvt/aperture_gm.c

+2 −2
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ static int alloc_resource(struct intel_vgpu *vgpu, 
}



/**

 * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU

 * intel_vgpu_free_resource() - free HW resource owned by a vGPU

 * @vgpu: a vGPU

 *

 * This function is used to free the HW resource owned by a vGPU.
@@ -328,7 +328,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu) 
}



/**

 * intel_alloc_vgpu_resource - allocate HW resource for a vGPU

 * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU

 * @vgpu: vGPU

 * @param: vGPU creation params

 *

drivers/gpu/drm/i915/gvt/gtt.c

+1 −1
Original line number Diff line number Diff line
@@ -2341,7 +2341,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 
			gvt_vgpu_err("fail to populate guest ggtt entry\n");

			/* guest driver may read/write the entry when partial

			 * update the entry in this situation p2m will fail

			 * settting the shadow entry to point to a scratch page

			 * setting the shadow entry to point to a scratch page

			 */

			ops->set_pfn(&m, gvt->gtt.scratch_mfn);

		} else

drivers/gpu/drm/i915/gvt/handlers.c

+2 −2
Original line number Diff line number Diff line
@@ -905,7 +905,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 
	else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)

		index = FDI_RX_IMR_TO_PIPE(offset);

	else {

		gvt_vgpu_err("Unsupport registers %x\n", offset);

		gvt_vgpu_err("Unsupported registers %x\n", offset);

		return -EINVAL;

	}
@@ -3052,7 +3052,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 
}



/**

 * intel_t_default_mmio_write - default MMIO write handler

 * intel_vgpu_default_mmio_write() - default MMIO write handler

 * @vgpu: a vGPU

 * @offset: access offset

 * @p_data: write data buffer

drivers/gpu/drm/i915/gvt/mmio_context.c

+1 −1
Original line number Diff line number Diff line
@@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre, 
}



/**

 * intel_gvt_switch_render_mmio - switch mmio context of specific engine

 * intel_gvt_switch_mmio - switch mmio context of specific engine

 * @pre: the last vGPU that own the engine

 * @next: the vGPU to switch to

 * @engine: the engine

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

+2 −1
Original line number Diff line number Diff line
@@ -1076,7 +1076,8 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) 
	MMIO_D(GEN8_HDC_CHICKEN1);

	MMIO_D(GEN9_WM_CHICKEN3);



	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))

	if (IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))

		MMIO_D(GAMT_CHKN_BIT_REG);

	if (!IS_BROXTON(dev_priv))

		MMIO_D(GEN9_CTX_PREEMPT_REG);