Commit 577f4258 authored Aug 13, 2021 by Krzysztof Kozlowski Committed by Rob Herring Aug 17, 2021

dt-bindings: memory: convert Qualcomm Atheros DDR to dtschema



Convert Qualcomm Atheros AR7xxx/AR9xxx DDR controller to DT schema
format using json-schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210813143537.130310-1-krzysztof.kozlowski@canonical.com


Signed-off-by: Rob Herring <robh@kernel.org>

parent 9634cec5

Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt

deleted100644 → 0

+0 −35

Original line number	Diff line number	Diff line
		Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller

		The DDR controller of the AR7xxx and AR9xxx families provides an interface
		to flush the FIFO between various devices and the DDR. This is mainly used
		by the IRQ controller to flush the FIFO before running the interrupt handler
		of such devices.

		Required properties:

		- compatible: has to be "qca,<soc-type>-ddr-controller",
		"qca,[ar7100\|ar7240]-ddr-controller" as fallback.
		On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
		fallback, otherwise "qca,ar7240-ddr-controller" should be used.
		- reg: Base address and size of the controller's memory area
		- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
		the write buffer channel index, should be 1.

		Example:

		ddr_ctrl: memory-controller@18000000 {
		compatible = "qca,ar9132-ddr-controller",
		"qca,ar7240-ddr-controller";
		reg = <0x18000000 0x100>;

		#qca,ddr-wb-channel-cells = <1>;
		};

		...

		interrupt-controller {
		...
		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
		<&ddr_ctrl 0>, <&ddr_ctrl 1>;
		};

Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml

0 → 100644

+61 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: GPL-2.0
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller

		maintainers:
		- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

		description: \|
		The DDR controller of the AR7xxx and AR9xxx families provides an interface to
		flush the FIFO between various devices and the DDR. This is mainly used by
		the IRQ controller to flush the FIFO before running the interrupt handler of
		such devices.

		properties:
		compatible:
		oneOf:
		- items:
		- const: qca,ar9132-ddr-controller
		- const: qca,ar7240-ddr-controller
		- items:
		- enum:
		- qca,ar7100-ddr-controller
		- qca,ar7240-ddr-controller

		"#qca,ddr-wb-channel-cells":
		description: \|
		Specifies the number of cells needed to encode the write buffer channel
		index.
		$ref: /schemas/types.yaml#/definitions/uint32
		const: 1

		reg:
		maxItems: 1

		required:
		- compatible
		- "#qca,ddr-wb-channel-cells"
		- reg

		additionalProperties: false

		examples:
		- \|
		ddr_ctrl: memory-controller@18000000 {
		compatible = "qca,ar9132-ddr-controller",
		"qca,ar7240-ddr-controller";
		reg = <0x18000000 0x100>;

		#qca,ddr-wb-channel-cells = <1>;
		};

		interrupt-controller {
		// ...
		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
		<&ddr_ctrl 0>, <&ddr_ctrl 1>;
		};