Commit 5745d647 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.14-2021-06-02' of... 

Merge tag 'amd-drm-next-5.14-2021-06-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.14-2021-06-02:

amdgpu:
- GC/MM register access macro clean up for SR-IOV
- Beige Goby updates
- W=1 Fixes
- Aldebaran fixes
- Misc display fixes
- ACPI ATCS/ATIF handling rework
- SR-IOV fixes
- RAS fixes
- 16bpc fixed point format support
- Initial smartshift support
- RV/PCO power tuning fixes for suspend/resume
- More buffer object subclassing work
- Add new INFO query for additional vbios information
- Add new placement for preemptable SG buffers

amdkfd:
- Misc fixes

radeon:
- W=1 Fixes
- Misc cleanups

UAPI:
- Add new INFO query for additional vbios information
  Useful for debugging vbios related issues.  Proposed umr patch:
  https://patchwork.freedesktop.org/patch/433297/
- 16bpc fixed point format support
  IGT test:
  https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html
  Proposed Vulkan patch:
  https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4


- Add a new GEM flag which is only used internally in the kernel driver.  Userspace
  is not allowed to set it.

drm:
- 16bpc fixed point format fourcc

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210602214009.4553-1-alexander.deucher@amd.com
parents ccd1950c 7d9c70d2

drivers/gpu/drm/amd/amdgpu/Makefile

+4 −3
Original line number Diff line number Diff line
@@ -51,9 +51,10 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \

	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \

	amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \

	amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o \

	amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+1 −1
Original line number Diff line number Diff line
@@ -227,7 +227,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 
			break;

		default:

			break;

		};

		}

	}



	/* Reinit NBIF block */

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+28 −19
Original line number Diff line number Diff line
@@ -130,6 +130,13 @@ struct amdgpu_mgpu_info 
	bool				pending_reset;

};



enum amdgpu_ss {

	AMDGPU_SS_DRV_LOAD,

	AMDGPU_SS_DEV_D0,

	AMDGPU_SS_DEV_D3,

	AMDGPU_SS_DRV_UNLOAD

};



struct amdgpu_watchdog_timer

{

	bool timeout_fatal_disable;
@@ -268,7 +275,6 @@ struct amdgpu_job; 
struct amdgpu_irq_src;

struct amdgpu_fpriv;

struct amdgpu_bo_va_mapping;

struct amdgpu_atif;

struct kfd_vm_fault_info;

struct amdgpu_hive_info;

struct amdgpu_reset_context;
@@ -682,20 +688,6 @@ struct amdgpu_vram_scratch { 
	u64				gpu_addr;

};



/*

 * ACPI

 */

struct amdgpu_atcs_functions {

	bool get_ext_state;

	bool pcie_perf_req;

	bool pcie_dev_rdy;

	bool pcie_bus_width;

};



struct amdgpu_atcs {

	struct amdgpu_atcs_functions functions;

};



/*

 * CGS

 */
@@ -825,8 +817,6 @@ struct amdgpu_device { 
	struct notifier_block		acpi_nb;

	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];

	struct debugfs_blob_wrapper     debugfs_vbios_blob;

	struct amdgpu_atif		*atif;

	struct amdgpu_atcs		atcs;

	struct mutex			srbm_mutex;

	/* GRBM index mutex. Protects concurrent access to GRBM index */

	struct mutex                    grbm_idx_mutex;
@@ -1146,6 +1136,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
 * Registers read & write functions.

 */

#define AMDGPU_REGS_NO_KIQ    (1<<1)

#define AMDGPU_REGS_RLC	(1<<2)



#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
@@ -1282,6 +1273,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 
bool amdgpu_device_supports_atpx(struct drm_device *dev);

bool amdgpu_device_supports_px(struct drm_device *dev);

bool amdgpu_device_supports_boco(struct drm_device *dev);

bool amdgpu_device_supports_smart_shift(struct drm_device *dev);

bool amdgpu_device_supports_baco(struct drm_device *dev);

bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,

				      struct amdgpu_device *peer_adev);
@@ -1356,21 +1348,38 @@ struct amdgpu_afmt_acr { 
struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);



/* amdgpu_acpi.c */



/* ATCS Device/Driver State */

#define AMDGPU_ATCS_PSC_DEV_STATE_D0		0

#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT	3

#define AMDGPU_ATCS_PSC_DRV_STATE_OPR		0

#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR	1



#if defined(CONFIG_ACPI)

int amdgpu_acpi_init(struct amdgpu_device *adev);

void amdgpu_acpi_fini(struct amdgpu_device *adev);

bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);

bool amdgpu_acpi_is_power_shift_control_supported(void);

int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,

						u8 perf_req, bool advertise);

int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,

				    u8 dev_state, bool drv_state);

int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);

int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);



void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,

		struct amdgpu_dm_backlight_caps *caps);

void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);

bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);

void amdgpu_acpi_detect(void);

#else

static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }

static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }

static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; }

static inline void amdgpu_acpi_detect(void) { }

static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }

static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,

						  u8 dev_state, bool drv_state) { return 0; }

static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,

						 enum amdgpu_ss ss_state) { return 0; }

#endif



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+262 −126
Original line number Diff line number Diff line
@@ -71,12 +71,31 @@ struct amdgpu_atif { 
	struct amdgpu_dm_backlight_caps backlight_caps;

};



struct amdgpu_atcs_functions {

	bool get_ext_state;

	bool pcie_perf_req;

	bool pcie_dev_rdy;

	bool pcie_bus_width;

	bool power_shift_control;

};



struct amdgpu_atcs {

	acpi_handle handle;



	struct amdgpu_atcs_functions functions;

};



static struct amdgpu_acpi_priv {

	struct amdgpu_atif atif;

	struct amdgpu_atcs atcs;

} amdgpu_acpi_priv;



/* Call the ATIF method

 */

/**

 * amdgpu_atif_call - call an ATIF method

 *

 * @atif: acpi handle

 * @atif: atif structure

 * @function: the ATIF function to execute

 * @params: ATIF function params

 *
@@ -207,35 +226,6 @@ static int amdgpu_atif_verify_interface(struct amdgpu_atif *atif) 
	return err;

}



static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle)

{

	acpi_handle handle = NULL;

	char acpi_method_name[255] = { 0 };

	struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name };

	acpi_status status;



	/* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on dGPU only

	 * systems, ATIF is in the dGPU's namespace.

	 */

	status = acpi_get_handle(dhandle, "ATIF", &handle);

	if (ACPI_SUCCESS(status))

		goto out;



	if (amdgpu_has_atpx()) {

		status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF",

					 &handle);

		if (ACPI_SUCCESS(status))

			goto out;

	}



	DRM_DEBUG_DRIVER("No ATIF handle found\n");

	return NULL;

out:

	acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);

	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);

	return handle;

}



/**

 * amdgpu_atif_get_notification_params - determine notify configuration

 *
@@ -414,7 +404,7 @@ static int amdgpu_atif_get_sbios_requests(struct amdgpu_atif *atif, 
static int amdgpu_atif_handler(struct amdgpu_device *adev,

			       struct acpi_bus_event *event)

{

	struct amdgpu_atif *atif = adev->atif;

	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;

	int count;



	DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n",
@@ -424,8 +414,7 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, 
		return NOTIFY_DONE;



	/* Is this actually our event? */

	if (!atif ||

	    !atif->notification_cfg.enabled ||

	if (!atif->notification_cfg.enabled ||

	    event->type != atif->notification_cfg.command_code) {

		/* These events will generate keypresses otherwise */

		if (event->type == ACPI_VIDEO_NOTIFY_PROBE)
@@ -485,14 +474,15 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev, 
/**

 * amdgpu_atcs_call - call an ATCS method

 *

 * @handle: acpi handle

 * @atcs: atcs structure

 * @function: the ATCS function to execute

 * @params: ATCS function params

 *

 * Executes the requested ATCS function (all asics).

 * Returns a pointer to the acpi output buffer.

 */

static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function,

static union acpi_object *amdgpu_atcs_call(struct amdgpu_atcs *atcs,

					   int function,

					   struct acpi_buffer *params)

{

	acpi_status status;
@@ -516,7 +506,7 @@ static union acpi_object *amdgpu_atcs_call(acpi_handle handle, int function, 
		atcs_arg_elements[1].integer.value = 0;

	}



	status = acpi_evaluate_object(handle, "ATCS", &atcs_arg, &buffer);

	status = acpi_evaluate_object(atcs->handle, NULL, &atcs_arg, &buffer);



	/* Fail only if calling the method fails and ATIF is supported */

	if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
@@ -545,12 +535,12 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas 
	f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED;

	f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED;

	f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED;

	f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED;

}



/**

 * amdgpu_atcs_verify_interface - verify ATCS

 *

 * @handle: acpi handle

 * @atcs: amdgpu atcs struct

 *

 * Execute the ATCS_FUNCTION_VERIFY_INTERFACE ATCS function
@@ -558,15 +548,14 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas 
 * (all asics).

 * returns 0 on success, error on failure.

 */

static int amdgpu_atcs_verify_interface(acpi_handle handle,

					struct amdgpu_atcs *atcs)

static int amdgpu_atcs_verify_interface(struct amdgpu_atcs *atcs)

{

	union acpi_object *info;

	struct atcs_verify_interface output;

	size_t size;

	int err = 0;



	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_VERIFY_INTERFACE, NULL);

	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_VERIFY_INTERFACE, NULL);

	if (!info)

		return -EIO;
@@ -603,7 +592,7 @@ static int amdgpu_atcs_verify_interface(acpi_handle handle, 
 */

bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev)

{

	struct amdgpu_atcs *atcs = &adev->atcs;

	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;



	if (atcs->functions.pcie_perf_req && atcs->functions.pcie_dev_rdy)

		return true;
@@ -611,6 +600,18 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade 
	return false;

}



/**

 * amdgpu_acpi_is_power_shift_control_supported

 *

 * Check if the ATCS power shift control method

 * is supported.

 * returns true if supported, false if not.

 */

bool amdgpu_acpi_is_power_shift_control_supported(void)

{

	return amdgpu_acpi_priv.atcs.functions.power_shift_control;

}



/**

 * amdgpu_acpi_pcie_notify_device_ready

 *
@@ -622,19 +623,13 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade 
 */

int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev)

{

	acpi_handle handle;

	union acpi_object *info;

	struct amdgpu_atcs *atcs = &adev->atcs;



	/* Get the device handle */

	handle = ACPI_HANDLE(&adev->pdev->dev);

	if (!handle)

		return -EINVAL;

	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;



	if (!atcs->functions.pcie_dev_rdy)

		return -EINVAL;



	info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL);

	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION, NULL);

	if (!info)

		return -EIO;
@@ -657,9 +652,8 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev) 
int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,

					 u8 perf_req, bool advertise)

{

	acpi_handle handle;

	union acpi_object *info;

	struct amdgpu_atcs *atcs = &adev->atcs;

	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;

	struct atcs_pref_req_input atcs_input;

	struct atcs_pref_req_output atcs_output;

	struct acpi_buffer params;
@@ -669,11 +663,6 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 
	if (amdgpu_acpi_pcie_notify_device_ready(adev))

		return -EINVAL;



	/* Get the device handle */

	handle = ACPI_HANDLE(&adev->pdev->dev);

	if (!handle)

		return -EINVAL;



	if (!atcs->functions.pcie_perf_req)

		return -EINVAL;
@@ -691,7 +680,7 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 
	params.pointer = &atcs_input;



	while (retry--) {

		info = amdgpu_atcs_call(handle, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, &params);

		info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST, &params);

		if (!info)

			return -EIO;
@@ -724,6 +713,96 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 
	return 0;

}



/**

 * amdgpu_acpi_power_shift_control

 *

 * @adev: amdgpu_device pointer

 * @dev_state: device acpi state

 * @drv_state: driver state

 *

 * Executes the POWER_SHIFT_CONTROL method to

 * communicate current dGPU device state and

 * driver state to APU/SBIOS.

 * returns 0 on success, error on failure.

 */

int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,

				    u8 dev_state, bool drv_state)

{

	union acpi_object *info;

	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;

	struct atcs_pwr_shift_input atcs_input;

	struct acpi_buffer params;



	if (!amdgpu_acpi_is_power_shift_control_supported())

		return -EINVAL;



	atcs_input.size = sizeof(struct atcs_pwr_shift_input);

	/* dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */

	atcs_input.dgpu_id = adev->pdev->devfn | (adev->pdev->bus->number << 8);

	atcs_input.dev_acpi_state = dev_state;

	atcs_input.drv_state = drv_state;



	params.length = sizeof(struct atcs_pwr_shift_input);

	params.pointer = &atcs_input;



	info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_POWER_SHIFT_CONTROL, &params);

	if (!info) {

		DRM_ERROR("ATCS PSC update failed\n");

		return -EIO;

	}



	return 0;

}



/**

 * amdgpu_acpi_smart_shift_update - update dGPU device state to SBIOS

 *

 * @dev: drm_device pointer

 * @ss_state: current smart shift event

 *

 * returns 0 on success,

 * otherwise return error number.

 */

int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state)

{

	struct amdgpu_device *adev = drm_to_adev(dev);

	int r;



	if (!amdgpu_device_supports_smart_shift(dev))

		return 0;



	switch (ss_state) {

	/* SBIOS trigger “stop”, “enable” and “start” at D0, Driver Operational.

	 * SBIOS trigger “stop” at D3, Driver Not Operational.

	 * SBIOS trigger “stop” and “disable” at D0, Driver NOT operational.

	 */

	case AMDGPU_SS_DRV_LOAD:

		r = amdgpu_acpi_power_shift_control(adev,

						    AMDGPU_ATCS_PSC_DEV_STATE_D0,

						    AMDGPU_ATCS_PSC_DRV_STATE_OPR);

		break;

	case AMDGPU_SS_DEV_D0:

		r = amdgpu_acpi_power_shift_control(adev,

						    AMDGPU_ATCS_PSC_DEV_STATE_D0,

						    AMDGPU_ATCS_PSC_DRV_STATE_OPR);

		break;

	case AMDGPU_SS_DEV_D3:

		r = amdgpu_acpi_power_shift_control(adev,

						    AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT,

						    AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);

		break;

	case AMDGPU_SS_DRV_UNLOAD:

		r = amdgpu_acpi_power_shift_control(adev,

						    AMDGPU_ATCS_PSC_DEV_STATE_D0,

						    AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR);

		break;

	default:

		return -EINVAL;

	}



	return r;

}



/**

 * amdgpu_acpi_event - handle notify events

 *
@@ -767,49 +846,14 @@ static int amdgpu_acpi_event(struct notifier_block *nb, 
 */

int amdgpu_acpi_init(struct amdgpu_device *adev)

{

	acpi_handle handle, atif_handle;

	struct amdgpu_atif *atif;

	struct amdgpu_atcs *atcs = &adev->atcs;

	int ret;



	/* Get the device handle */

	handle = ACPI_HANDLE(&adev->pdev->dev);



	if (!adev->bios || !handle)

		return 0;



	/* Call the ATCS method */

	ret = amdgpu_atcs_verify_interface(handle, atcs);

	if (ret) {

		DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret);

	}



	/* Probe for ATIF, and initialize it if found */

	atif_handle = amdgpu_atif_probe_handle(handle);

	if (!atif_handle)

		goto out;



	atif = kzalloc(sizeof(*atif), GFP_KERNEL);

	if (!atif) {

		DRM_WARN("Not enough memory to initialize ATIF\n");

		goto out;

	}

	atif->handle = atif_handle;



	/* Call the ATIF method */

	ret = amdgpu_atif_verify_interface(atif);

	if (ret) {

		DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret);

		kfree(atif);

		goto out;

	}

	adev->atif = atif;

	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;



#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

	if (atif->notifications.brightness_change) {

		if (amdgpu_device_has_dc_support(adev)) {

#if defined(CONFIG_DRM_AMD_DC)

			struct amdgpu_display_manager *dm = &adev->dm;

			if (dm->backlight_dev)

				atif->bd = dm->backlight_dev;

#endif

		} else {
@@ -832,6 +876,129 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) 
		}

	}

#endif

	adev->acpi_nb.notifier_call = amdgpu_acpi_event;

	register_acpi_notifier(&adev->acpi_nb);



	return 0;

}



void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps)

{

	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;



	caps->caps_valid = atif->backlight_caps.caps_valid;

	caps->min_input_signal = atif->backlight_caps.min_input_signal;

	caps->max_input_signal = atif->backlight_caps.max_input_signal;

}



/**

 * amdgpu_acpi_fini - tear down driver acpi support

 *

 * @adev: amdgpu_device pointer

 *

 * Unregisters with the acpi notifier chain (all asics).

 */

void amdgpu_acpi_fini(struct amdgpu_device *adev)

{

	unregister_acpi_notifier(&adev->acpi_nb);

}



/**

 * amdgpu_atif_pci_probe_handle - look up the ATIF handle

 *

 * @pdev: pci device

 *

 * Look up the ATIF handles (all asics).

 * Returns true if the handle is found, false if not.

 */

static bool amdgpu_atif_pci_probe_handle(struct pci_dev *pdev)

{

	char acpi_method_name[255] = { 0 };

	struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};

	acpi_handle dhandle, atif_handle;

	acpi_status status;

	int ret;



	dhandle = ACPI_HANDLE(&pdev->dev);

	if (!dhandle)

		return false;



	status = acpi_get_handle(dhandle, "ATIF", &atif_handle);

	if (ACPI_FAILURE(status)) {

		return false;

	}

	amdgpu_acpi_priv.atif.handle = atif_handle;

	acpi_get_name(amdgpu_acpi_priv.atif.handle, ACPI_FULL_PATHNAME, &buffer);

	DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);

	ret = amdgpu_atif_verify_interface(&amdgpu_acpi_priv.atif);

	if (ret) {

		amdgpu_acpi_priv.atif.handle = 0;

		return false;

	}

	return true;

}



/**

 * amdgpu_atcs_pci_probe_handle - look up the ATCS handle

 *

 * @pdev: pci device

 *

 * Look up the ATCS handles (all asics).

 * Returns true if the handle is found, false if not.

 */

static bool amdgpu_atcs_pci_probe_handle(struct pci_dev *pdev)

{

	char acpi_method_name[255] = { 0 };

	struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name };

	acpi_handle dhandle, atcs_handle;

	acpi_status status;

	int ret;



	dhandle = ACPI_HANDLE(&pdev->dev);

	if (!dhandle)

		return false;



	status = acpi_get_handle(dhandle, "ATCS", &atcs_handle);

	if (ACPI_FAILURE(status)) {

		return false;

	}

	amdgpu_acpi_priv.atcs.handle = atcs_handle;

	acpi_get_name(amdgpu_acpi_priv.atcs.handle, ACPI_FULL_PATHNAME, &buffer);

	DRM_DEBUG_DRIVER("Found ATCS handle %s\n", acpi_method_name);

	ret = amdgpu_atcs_verify_interface(&amdgpu_acpi_priv.atcs);

	if (ret) {

		amdgpu_acpi_priv.atcs.handle = 0;

		return false;

	}

	return true;

}



/*

 * amdgpu_acpi_detect - detect ACPI ATIF/ATCS methods

 *

 * Check if we have the ATIF/ATCS methods and populate

 * the structures in the driver.

 */

void amdgpu_acpi_detect(void)

{

	struct amdgpu_atif *atif = &amdgpu_acpi_priv.atif;

	struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs;

	struct pci_dev *pdev = NULL;

	int ret;



	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {

		if (!atif->handle)

			amdgpu_atif_pci_probe_handle(pdev);

		if (!atcs->handle)

			amdgpu_atcs_pci_probe_handle(pdev);

	}



	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {

		if (!atif->handle)

			amdgpu_atif_pci_probe_handle(pdev);

		if (!atcs->handle)

			amdgpu_atcs_pci_probe_handle(pdev);

	}



	if (atif->functions.sbios_requests && !atif->functions.system_params) {

		/* XXX check this workraround, if sbios request function is
@@ -861,37 +1028,6 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) 
	} else {

		atif->backlight_caps.caps_valid = false;

	}



out:

	adev->acpi_nb.notifier_call = amdgpu_acpi_event;

	register_acpi_notifier(&adev->acpi_nb);



	return ret;

}



void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,

		struct amdgpu_dm_backlight_caps *caps)

{

	if (!adev->atif) {

		caps->caps_valid = false;

		return;

	}

	caps->caps_valid = adev->atif->backlight_caps.caps_valid;

	caps->min_input_signal = adev->atif->backlight_caps.min_input_signal;

	caps->max_input_signal = adev->atif->backlight_caps.max_input_signal;

}



/**

 * amdgpu_acpi_fini - tear down driver acpi support

 *

 * @adev: amdgpu_device pointer

 *

 * Unregisters with the acpi notifier chain (all asics).

 */

void amdgpu_acpi_fini(struct amdgpu_device *adev)

{

	unregister_acpi_notifier(&adev->acpi_nb);

	kfree(adev->atif);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+21 −21
Original line number Diff line number Diff line
@@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 


	lock_srbm(kgd, 0, 0, 0, vmid);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);

	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);

	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);

	/* APE1 no longer exists on GFX9 */



	unlock_srbm(kgd);
@@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 


	lock_srbm(kgd, mec, pipe, 0, 0);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),

	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,

		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
@@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 


	for (reg = hqd_base;

	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

		WREG32(reg, mqd_hqd[reg - hqd_base]);

		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);





	/* Activate doorbell logic before triggering WPTR poll. */

	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);

	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);



	if (wptr) {

		/* Don't read wptr with get_user because the user
@@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 
		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);

		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;



		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,

		       lower_32_bits(guessed_wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

		       upper_32_bits(guessed_wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,

		       lower_32_bits((uint64_t)wptr));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,

		       upper_32_bits((uint64_t)wptr));

		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,

			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));

		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,

		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));

	}



	/* Start the EOP fetcher */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),

	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,

	       REG_SET_FIELD(m->cp_hqd_eop_rptr,

			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));



	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);

	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);



	release_queue(kgd);
@@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd, 
		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\

			break;				\

		(*dump)[i][0] = (addr) << 2;		\

		(*dump)[i++][1] = RREG32(addr);		\

		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\

	} while (0)



	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 
	uint32_t low, high;



	acquire_queue(kgd, pipe_id, queue_id);

	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

	if (act) {

		low = lower_32_bits(queue_address >> 8);

		high = upper_32_bits(queue_address >> 8);



		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&

		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))

		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

			retval = true;

	}

	release_queue(kgd);
@@ -621,11 +621,11 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 
	preempt_enable();

#endif



	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);

	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);



	end_jiffies = (utimeout * HZ / 1000) + jiffies;

	while (true) {

		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));

		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))

			break;

		if (time_after(jiffies, end_jiffies)) {
@@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, 


	mutex_lock(&adev->grbm_idx_mutex);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);

	WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);



	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

		INSTANCE_BROADCAST_WRITES, 1);
@@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd, 
	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

		SE_BROADCAST_WRITES, 1);



	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

	mutex_unlock(&adev->grbm_idx_mutex);



	return 0;