Commit 572f2a5c authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Matt Roper
Browse files

drm/i915/guc: Update firmware to v62.0.0 



Most of the changes to the 62.0.0 firmware revolved around CTB
communication channel. Conform to the new (stable) CTB protocol.

v2:
 (Michal)
  Add values back to kernel DOC for actions
 (Docs)
  Add 'CT buffer' back in to fix warning

Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
[mattrope: Tweaked kerneldoc while pushing as suggested by Daniele/Michal]
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210616001302.84233-3-matthew.brost@intel.com
parent 088b4d4a

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

+107 −0
Original line number Diff line number Diff line
@@ -6,6 +6,113 @@ 
#ifndef _ABI_GUC_ACTIONS_ABI_H

#define _ABI_GUC_ACTIONS_ABI_H



/**

 * DOC: HOST2GUC_REGISTER_CTB

 *

 * This message is used as part of the `CTB based communication`_ setup.

 *

 * This message must be sent as `MMIO HXG Message`_.

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 27:16 | DATA0 = MBZ                                                  |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505        |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 | 31:12 | RESERVED = MBZ                                               |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | **TYPE** - type for the `CT Buffer`_                         |

 *  |   |       |                                                              |

 *  |   |       |   - _`GUC_CTB_TYPE_HOST2GUC` = 0                             |

 *  |   |       |   - _`GUC_CTB_TYPE_GUC2HOST` = 1                             |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | **SIZE** - size of the `CT Buffer`_ in 4K units minus 1      |

 *  +---+-------+--------------------------------------------------------------+

 *  | 2 |  31:0 | **DESC_ADDR** - GGTT address of the `CTB Descriptor`_        |

 *  +---+-------+--------------------------------------------------------------+

 *  | 3 |  31:0 | **BUFF_ADDF** - GGTT address of the `CT Buffer`_             |

 *  +---+-------+--------------------------------------------------------------+

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  27:0 | DATA0 = MBZ                                                  |

 *  +---+-------+--------------------------------------------------------------+

 */

#define GUC_ACTION_HOST2GUC_REGISTER_CTB		0x4505



#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_MBZ		(0xfffff << 12)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)

#define   GUC_CTB_TYPE_HOST2GUC				0u

#define   GUC_CTB_TYPE_GUC2HOST				1u

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_SIZE	(0xff << 0)

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_3_BUFF_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn



#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0



/**

 * DOC: HOST2GUC_DEREGISTER_CTB

 *

 * This message is used as part of the `CTB based communication`_ teardown.

 *

 * This message must be sent as `MMIO HXG Message`_.

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 27:16 | DATA0 = MBZ                                                  |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_DEREGISTER_CTB` = 0x4506      |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 | 31:12 | RESERVED = MBZ                                               |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | **TYPE** - type of the `CT Buffer`_                          |

 *  |   |       |                                                              |

 *  |   |       | see `GUC_ACTION_HOST2GUC_REGISTER_CTB`_                      |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | RESERVED = MBZ                                               |

 *  +---+-------+--------------------------------------------------------------+

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  27:0 | DATA0 = MBZ                                                  |

 *  +---+-------+--------------------------------------------------------------+

 */

#define GUC_ACTION_HOST2GUC_DEREGISTER_CTB		0x4506



#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_0_MBZ	GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ	(0xfffff << 12)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)

#define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ2	(0xff << 0)



#define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_LEN	GUC_HXG_RESPONSE_MSG_MIN_LEN

#define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0



/* legacy definitions */



enum intel_guc_action {

	INTEL_GUC_ACTION_DEFAULT = 0x0,

	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,

drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h

+104 −22
Original line number Diff line number Diff line
@@ -7,6 +7,110 @@ 
#define _ABI_GUC_COMMUNICATION_CTB_ABI_H



#include <linux/types.h>

#include <linux/build_bug.h>



#include "guc_messages_abi.h"



/**

 * DOC: CT Buffer

 *

 * Circular buffer used to send `CTB Message`_

 */



/**

 * DOC: CTB Descriptor

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |  31:0 | **HEAD** - offset (in dwords) to the last dword that was     |

 *  |   |       | read from the `CT Buffer`_.                                  |

 *  |   |       | It can only be updated by the receiver.                      |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 |  31:0 | **TAIL** - offset (in dwords) to the last dword that was     |

 *  |   |       | written to the `CT Buffer`_.                                 |

 *  |   |       | It can only be updated by the sender.                        |

 *  +---+-------+--------------------------------------------------------------+

 *  | 2 |  31:0 | **STATUS** - status of the CTB                               |

 *  |   |       |                                                              |

 *  |   |       |   - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)        |

 *  |   |       |   - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large)     |

 *  |   |       |   - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)      |

 *  |   |       |   - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)      |

 *  +---+-------+--------------------------------------------------------------+

 *  |...|       | RESERVED = MBZ                                               |

 *  +---+-------+--------------------------------------------------------------+

 *  | 15|  31:0 | RESERVED = MBZ                                               |

 *  +---+-------+--------------------------------------------------------------+

 */



struct guc_ct_buffer_desc {

	u32 head;

	u32 tail;

	u32 status;

#define GUC_CTB_STATUS_NO_ERROR				0

#define GUC_CTB_STATUS_OVERFLOW				(1 << 0)

#define GUC_CTB_STATUS_UNDERFLOW			(1 << 1)

#define GUC_CTB_STATUS_MISMATCH				(1 << 2)

	u32 reserved[13];

} __packed;

static_assert(sizeof(struct guc_ct_buffer_desc) == 64);



/**

 * DOC: CTB Message

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 | 31:16 | **FENCE** - message identifier                               |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 15:12 | **FORMAT** - format of the CTB message                       |

 *  |   |       |  - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_        |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | **RESERVED**                                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | **NUM_DWORDS** - length of the CTB message (w/o header)      |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 |  31:0 | optional (depends on FORMAT)                                 |

 *  +---+-------+                                                              |

 *  |...|       |                                                              |

 *  +---+-------+                                                              |

 *  | n |  31:0 |                                                              |

 *  +---+-------+--------------------------------------------------------------+

 */



#define GUC_CTB_MSG_MIN_LEN			1u

#define GUC_CTB_MSG_MAX_LEN			256u

#define GUC_CTB_MSG_0_FENCE			(0xffff << 16)

#define GUC_CTB_MSG_0_FORMAT			(0xf << 12)

#define   GUC_CTB_FORMAT_HXG			0u

#define GUC_CTB_MSG_0_RESERVED			(0xf << 8)

#define GUC_CTB_MSG_0_NUM_DWORDS		(0xff << 0)



/**

 * DOC: CTB HXG Message

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 | 31:16 | FENCE                                                        |

 *  |   +-------+--------------------------------------------------------------+

 *  |   | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_                                 |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |  11:8 | RESERVED = MBZ                                               |

 *  |   +-------+--------------------------------------------------------------+

 *  |   |   7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message  |

 *  +---+-------+--------------------------------------------------------------+

 *  | 1 |  31:0 |  +--------------------------------------------------------+  |

 *  +---+-------+  |                                                        |  |

 *  |...|       |  |  Embedded `HXG Message`_                               |  |

 *  +---+-------+  |                                                        |  |

 *  | n |  31:0 |  +--------------------------------------------------------+  |

 *  +---+-------+--------------------------------------------------------------+

 */



#define GUC_CTB_HXG_MSG_MIN_LEN		(GUC_CTB_MSG_MIN_LEN + GUC_HXG_MSG_MIN_LEN)

#define GUC_CTB_HXG_MSG_MAX_LEN		GUC_CTB_MSG_MAX_LEN



/**

 * DOC: CTB based communication
@@ -60,28 +164,6 @@ 
 * - **flags**, holds various bits to control message handling

 */



/*

 * Describes single command transport buffer.

 * Used by both guc-master and clients.

 */

struct guc_ct_buffer_desc {

	u32 addr;		/* gfx address */

	u64 host_private;	/* host private data */

	u32 size;		/* size in bytes */

	u32 head;		/* offset updated by GuC*/

	u32 tail;		/* offset updated by owner */

	u32 is_in_error;	/* error indicator */

	u32 reserved1;

	u32 reserved2;

	u32 owner;		/* id of the channel owner */

	u32 owner_sub_id;	/* owner-defined field for extra tracking */

	u32 reserved[5];

} __packed;



/* Type of command transport buffer */

#define INTEL_GUC_CT_BUFFER_TYPE_SEND	0x0u

#define INTEL_GUC_CT_BUFFER_TYPE_RECV	0x1u



/*

 * Definition of the command transport message header (DW0)

 *

drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h

+31 −34
Original line number Diff line number Diff line
@@ -7,46 +7,43 @@ 
#define _ABI_GUC_COMMUNICATION_MMIO_ABI_H



/**

 * DOC: MMIO based communication

 * DOC: GuC MMIO based communication

 *

 * The MMIO based communication between Host and GuC uses software scratch

 * registers, where first register holds data treated as message header,

 * and other registers are used to hold message payload.

 * The MMIO based communication between Host and GuC relies on special

 * hardware registers which format could be defined by the software

 * (so called scratch registers).

 *

 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,

 * but no H2G command takes more than 8 parameters and the GuC FW

 * itself uses an 8-element array to store the H2G message.

 * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)

 * messages, which maximum length depends on number of available scratch

 * registers, is directly written into those scratch registers.

 *

 *      +-----------+---------+---------+---------+

 *      |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |

 *      +-----------+---------+---------+---------+

 *      | header    |      optional payload       |

 *      +======+====+=========+=========+=========+

 *      | 31:28|type|         |         |         |

 *      +------+----+         |         |         |

 *      | 27:16|data|         |         |         |

 *      +------+----+         |         |         |

 *      |  15:0|code|         |         |         |

 *      +------+----+---------+---------+---------+

 * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,

 * but no H2G command takes more than 4 parameters and the GuC firmware

 * itself uses an 4-element array to store the H2G message.

 *

 * The message header consists of:

 * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which

 * are, regardless on lower count, preferred over legacy ones.

 *

 * - **type**, indicates message type

 * - **code**, indicates message code, is specific for **type**

 * - **data**, indicates message data, optional, depends on **code**

 *

 * The following message **types** are supported:

 *

 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code

 *   must be priovided in **code** field. Optional action specific parameters

 *   can be provided in remaining payload registers or **data** field.

 *

 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,

 *   action response status will be provided in **code** field. Optional

 *   response data can be returned in remaining payload registers or **data**

 *   field.

 * The MMIO based communication is mainly used during driver initialization

 * phase to setup the `CTB based communication`_ that will be used afterwards.

 */



#define GUC_MAX_MMIO_MSG_LEN		8

#define GUC_MAX_MMIO_MSG_LEN		4



/**

 * DOC: MMIO HXG Message

 *

 * Format of the MMIO messages follows definitions of `HXG Message`_.

 *

 *  +---+-------+--------------------------------------------------------------+

 *  |   | Bits  | Description                                                  |

 *  +===+=======+==============================================================+

 *  | 0 |  31:0 |  +--------------------------------------------------------+  |

 *  +---+-------+  |                                                        |  |

 *  |...|       |  |  Embedded `HXG Message`_                               |  |

 *  +---+-------+  |                                                        |  |

 *  | n |  31:0 |  +--------------------------------------------------------+  |

 *  +---+-------+--------------------------------------------------------------+

 */



#endif /* _ABI_GUC_COMMUNICATION_MMIO_ABI_H */

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+72 −35
Original line number Diff line number Diff line
@@ -219,24 +219,19 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) 


	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));

	BUILD_BUG_ON(!DPC_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));

	BUILD_BUG_ON(!ISR_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));

	BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);

	BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, UNIT));



	BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >

			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));

	BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >

			(GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));

	BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >

			(GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));

	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / UNIT - 1) >

			(GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));



	flags = GUC_LOG_VALID |

		GUC_LOG_NOTIFY_ON_HALF_FULL |

		FLAG |

		((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |

		((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |

		((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |

		((DEBUG_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |

		(offset << GUC_LOG_BUF_ADDR_SHIFT);



	#undef UNIT
@@ -376,29 +371,27 @@ void intel_guc_fini(struct intel_guc *guc) 
/*

 * This function implements the MMIO based host to GuC interface.

 */

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,

int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,

			u32 *response_buf, u32 response_buf_size)

{

	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;

	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;

	u32 status;

	u32 header;

	int i;

	int ret;



	GEM_BUG_ON(!len);

	GEM_BUG_ON(len > guc->send_regs.count);



	/* We expect only action code */

	GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);



	/* If CT is available, we expect to use MMIO only during init/fini */

	GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&

		   *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);

	GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST);

	GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST);



	mutex_lock(&guc->send_mutex);

	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);



retry:

	for (i = 0; i < len; i++)

		intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);

		intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]);



	intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
@@ -410,30 +403,74 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 
	 */

	ret = __intel_wait_for_register_fw(uncore,

					   guc_send_reg(guc, 0),

					   INTEL_GUC_MSG_TYPE_MASK,

					   INTEL_GUC_MSG_TYPE_RESPONSE <<

					   INTEL_GUC_MSG_TYPE_SHIFT,

					   10, 10, &status);

	/* If GuC explicitly returned an error, convert it to -EIO */

	if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))

		ret = -EIO;

					   GUC_HXG_MSG_0_ORIGIN,

					   FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,

						      GUC_HXG_ORIGIN_GUC),

					   10, 10, &header);

	if (unlikely(ret)) {

timeout:

		drm_err(&i915->drm, "mmio request %#x: no reply %x\n",

			request[0], header);

		goto out;

	}



	if (ret) {

		DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",

			  action[0], ret, status);

	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {

#define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \

		FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \

		FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; })



		ret = wait_for(done, 1000);

		if (unlikely(ret))

			goto timeout;

		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=

				       GUC_HXG_ORIGIN_GUC))

			goto proto;

#undef done

	}



	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {

		u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);



		drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",

			request[0], reason);

		goto retry;

	}



	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) {

		u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);

		u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);



		drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",

			request[0], error, hint);

		ret = -ENXIO;

		goto out;

	}



	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {

proto:

		drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",

			request[0], header);

		ret = -EPROTO;

		goto out;

	}



	if (response_buf) {

		int count = min(response_buf_size, guc->send_regs.count - 1);

		int count = min(response_buf_size, guc->send_regs.count);



		for (i = 0; i < count; i++)

		GEM_BUG_ON(!count);



		response_buf[0] = header;



		for (i = 1; i < count; i++)

			response_buf[i] = intel_uncore_read(uncore,

							    guc_send_reg(guc, i + 1));

	}

							    guc_send_reg(guc, i));



		/* Use number of copied dwords as our return value */

		ret = count;

	} else {

		/* Use data from the GuC response as our return value */

	ret = INTEL_GUC_MSG_TO_DATA(status);

		ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);

	}



out:

	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

+4 −41
Original line number Diff line number Diff line
@@ -24,10 +24,6 @@ 
 *      +---------------------------------------+

 *      | guc_gt_system_info                    |

 *      +---------------------------------------+

 *      | guc_clients_info                      |

 *      +---------------------------------------+

 *      | guc_ct_pool_entry[size]               |

 *      +---------------------------------------+

 *      | padding                               |

 *      +---------------------------------------+ <== 4K aligned

 *      | private data                          |
@@ -39,8 +35,6 @@ struct __guc_ads_blob { 
	struct guc_ads ads;

	struct guc_policies policies;

	struct guc_gt_system_info system_info;

	struct guc_clients_info clients_info;

	struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];

} __packed;



static u32 guc_ads_private_data_size(struct intel_guc *guc)
@@ -59,38 +53,15 @@ static u32 guc_ads_blob_size(struct intel_guc *guc) 
	       guc_ads_private_data_size(guc);

}



static void guc_policy_init(struct guc_policy *policy)

{

	policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;

	policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;

	policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;

	policy->policy_flags = 0;

}



static void guc_policies_init(struct guc_policies *policies)

{

	struct guc_policy *policy;

	u32 p, i;



	policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;

	policies->max_num_work_items = POLICY_MAX_NUM_WI;



	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {

		for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {

			policy = &policies->policy[p][i];



			guc_policy_init(policy);

		}

	}



	policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;

	policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;

	/* Disable automatic resets as not yet supported. */

	policies->global_flags = GLOBAL_POLICY_DISABLE_ENGINE_RESET;

	policies->is_valid = 1;

}



static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)

{

	memset(pool, 0, num * sizeof(*pool));

}



static void guc_mapping_table_init(struct intel_gt *gt,

				   struct guc_gt_system_info *system_info)

{
@@ -178,17 +149,9 @@ static void __guc_ads_init(struct intel_guc *guc) 


	base = intel_guc_ggtt_offset(guc, guc->ads_vma);



	/* Clients info  */

	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));



	blob->clients_info.clients_num = 1;

	blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);

	blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);



	/* ADS */

	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);

	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);

	blob->ads.clients_info = base + ptr_offset(blob, clients_info);



	/* Private Data */

	blob->ads.private_data = base + guc_ads_private_data_offset(guc);