Unverified Commit 570c14dc authored by Tinghan Shen's avatar Tinghan Shen Committed by Mark Brown
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ASoC: SOF: mediatek: Add mt8186 sof fw loader and dsp ops

parent 1f0214a8
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
snd-sof-mt8186-objs := mt8186.o
snd-sof-mt8186-objs := mt8186.o mt8186-loader.o
obj-$(CONFIG_SND_SOC_SOF_MT8186) += snd-sof-mt8186.o
+53 −0
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// Copyright (c) 2022 Mediatek Corporation. All rights reserved.
//
// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
//         Tinghan Shen <tinghan.shen@mediatek.com>
//
// Hardware interface for mt8186 DSP code loader

#include <sound/sof.h>
#include "mt8186.h"
#include "../../ops.h"

void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
{
	/* set RUNSTALL to stop core */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
				RUNSTALL, RUNSTALL);

	/* set core boot address */
	snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
	snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);

	/* assert core reset */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
				SW_RSTN_C0 | SW_DBG_RSTN_C0,
				SW_RSTN_C0 | SW_DBG_RSTN_C0);

	/* hardware requirement */
	udelay(1);

	/* release core reset */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
				SW_RSTN_C0 | SW_DBG_RSTN_C0,
				0);

	/* clear RUNSTALL (bit31) to start core */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
				RUNSTALL, 0);
}

void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
{
	/* set RUNSTALL to stop core */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
				RUNSTALL, RUNSTALL);

	/* assert core reset */
	snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
				SW_RSTN_C0 | SW_DBG_RSTN_C0,
				SW_RSTN_C0 | SW_DBG_RSTN_C0);
}
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@@ -204,6 +204,17 @@ static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
	return 0;
}

static int mt8186_run(struct snd_sof_dev *sdev)
{
	u32 adsp_bootup_addr;

	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
	sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);

	return 0;
}

static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
{
	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
@@ -272,6 +283,7 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)

static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
{
	sof_hifixdsp_shutdown(sdev);
	adsp_sram_power_off(sdev);

	return 0;
@@ -289,6 +301,9 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = {
	.probe		= mt8186_dsp_probe,
	.remove		= mt8186_dsp_remove,

	/* DSP core boot */
	.run		= mt8186_run,

	/* Block IO */
	.block_read	= sof_block_read,
	.block_write	= sof_block_write,
@@ -302,6 +317,9 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = {
	/* misc */
	.get_bar_index	= mt8186_get_bar_index,

	/* firmware loading */
	.load_firmware	= snd_sof_load_firmware_memcpy,

	/* Firmware ops */
	.dsp_arch_ops = &sof_xtensa_arch_ops,

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@@ -10,6 +10,7 @@
#define __MT8186_H

struct mtk_adsp_chip_info;
struct snd_sof_dev;

#define DSP_REG_BAR			4
#define DSP_SECREG_BAR			5
@@ -74,4 +75,6 @@ struct mtk_adsp_chip_info;
#define SIZE_SHARED_DRAM_UL			0x40000 /*Shared buffer for Uplink*/
#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL	(SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)

void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
#endif