Commit 56ebef0a authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/ctrl/xilinx-cpm' 

- Add DT binding and driver support for Versal CPM5 Gen5 Root Port (Bharat
  Kumar Gogada)

* pci/ctrl/xilinx-cpm:
  MAINTAINERS: Add Xilinx Versal CPM Root Port maintainers
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
parents a91c6db7 4e6217e3

Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

+37 −1
Original line number Diff line number Diff line
@@ -14,17 +14,23 @@ allOf: 


properties:

  compatible:

    const: xlnx,versal-cpm-host-1.00

    enum:

      - xlnx,versal-cpm-host-1.00

      - xlnx,versal-cpm5-host



  reg:

    items:

      - description: CPM system level control and status registers.

      - description: Configuration space region and bridge registers.

      - description: CPM5 control and status registers.

    minItems: 2



  reg-names:

    items:

      - const: cpm_slcr

      - const: cfg

      - const: cpm_csr

    minItems: 2



  interrupts:

    maxItems: 1
@@ -95,4 +101,34 @@ examples: 
                               interrupt-controller;

                       };

               };



               cpm5_pcie: pcie@fcdd0000 {

                       compatible = "xlnx,versal-cpm5-host";

                       device_type = "pci";

                       #address-cells = <3>;

                       #interrupt-cells = <1>;

                       #size-cells = <2>;

                       interrupts = <0 72 4>;

                       interrupt-parent = <&gic>;

                       interrupt-map-mask = <0 0 0 7>;

                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,

                                       <0 0 0 2 &pcie_intc_1 1>,

                                       <0 0 0 3 &pcie_intc_1 2>,

                                       <0 0 0 4 &pcie_intc_1 3>;

                       bus-range = <0x00 0xff>;

                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,

                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;

                       msi-map = <0x0 &its_gic 0x0 0x10000>;

                       reg = <0x00 0xfcdd0000 0x00 0x1000>,

                             <0x06 0x00000000 0x00 0x1000000>,

                             <0x00 0xfce20000 0x00 0x1000000>;

                       reg-names = "cpm_slcr", "cfg", "cpm_csr";



                       pcie_intc_1: interrupt-controller {

                               #address-cells = <0>;

                               #interrupt-cells = <1>;

                               interrupt-controller;

                       };

               };



    };

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -15540,6 +15540,14 @@ L: linux-pci@vger.kernel.org 
S:	Maintained

F:	drivers/pci/controller/dwc/*spear*









PCI DRIVER FOR XILINX VERSAL CPM









M:	Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>









M:	Michal Simek <michal.simek@amd.com>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml









F:	drivers/pci/controller/pcie-xilinx-cpm.c

















PCMCIA SUBSYSTEM









M:	Dominik Brodowski <linux@dominikbrodowski.net>









S:	Odd Fixes
































drivers/pci/controller/pcie-xilinx-cpm.c



+58
−2






























Original line number
Diff line number
Diff line







@@ -35,6 +35,10 @@







#define XILINX_CPM_PCIE_MISC_IR_ENABLE	0x00000348









#define XILINX_CPM_PCIE_MISC_IR_LOCAL	BIT(1)



















#define XILINX_CPM_PCIE_IR_STATUS       0x000002A0









#define XILINX_CPM_PCIE_IR_ENABLE       0x000002A8









#define XILINX_CPM_PCIE_IR_LOCAL        BIT(0)



















/* Interrupt registers definitions */









#define XILINX_CPM_PCIE_INTR_LINK_DOWN		0









#define XILINX_CPM_PCIE_INTR_HOT_RESET		3








@@ -98,6 +102,19 @@







/* Phy Status/Control Register definitions */









#define XILINX_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)



















enum xilinx_cpm_version {









	CPM,









	CPM5,









};



















/**









 * struct xilinx_cpm_variant - CPM variant information









 * @version: CPM version









 */









struct xilinx_cpm_variant {









	enum xilinx_cpm_version version;









};



















/**









 * struct xilinx_cpm_pcie - PCIe port information









 * @dev: Device pointer








@@ -109,6 +126,7 @@







 * @intx_irq: legacy interrupt number









 * @irq: Error interrupt number









 * @lock: lock protecting shared register access









 * @variant: CPM version check pointer









 */









struct xilinx_cpm_pcie {









	struct device			*dev;








@@ -120,6 +138,7 @@ struct xilinx_cpm_pcie {







	int				intx_irq;









	int				irq;









	raw_spinlock_t			lock;









	const struct xilinx_cpm_variant   *variant;









};



















static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)








@@ -285,6 +304,13 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)







		generic_handle_domain_irq(port->cpm_domain, i);









	pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);



















	if (port->variant->version == CPM5) {









		val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);









		if (val)









			writel_relaxed(val, port->cpm_base +









					    XILINX_CPM_PCIE_IR_STATUS);









	}



















	/*









	 * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to









	 * CPM SLCR block.








@@ -484,6 +510,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)







	 */









	writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,









	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);



















	if (port->variant->version == CPM5) {









		writel(XILINX_CPM_PCIE_IR_LOCAL,









		       port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);









	}



















	/* Enable the Bridge enable bit */









	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |









		   XILINX_CPM_PCIE_REG_RPSC_BEN,








@@ -518,7 +550,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,







	if (IS_ERR(port->cfg))









		return PTR_ERR(port->cfg);



















	if (port->variant->version == CPM5) {









		port->reg_base = devm_platform_ioremap_resource_byname(pdev,









								    "cpm_csr");









		if (IS_ERR(port->reg_base))









			return PTR_ERR(port->reg_base);









	} else {









		port->reg_base = port->cfg->win;









	}



















	return 0;









}








@@ -559,6 +598,8 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)







	if (!bus)









		return -ENODEV;



















	port->variant = of_device_get_match_data(dev);



















	err = xilinx_cpm_pcie_parse_dt(port, bus->res);









	if (err) {









		dev_err(dev, "Parsing DT failed\n");








@@ -591,8 +632,23 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)







	return err;









}



















static const struct xilinx_cpm_variant cpm_host = {









	.version = CPM,









};



















static const struct xilinx_cpm_variant cpm5_host = {









	.version = CPM5,









};



















static const struct of_device_id xilinx_cpm_pcie_of_match[] = {









	{ .compatible = "xlnx,versal-cpm-host-1.00", },









	{









		.compatible = "xlnx,versal-cpm-host-1.00",









		.data = &cpm_host,









	},









	{









		.compatible = "xlnx,versal-cpm5-host",









		.data = &cpm5_host,









	},









	{}









};