Commit 56bf858e authored by Amelie Delaunay's avatar Amelie Delaunay Committed by Vinod Koul
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phy: stm32: ensure pll is disabled before phys creation 



To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.

Signed-off-by: default avatarAmelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 04edf6d6

drivers/phy/st/phy-stm32-usbphyc.c

+15 −2
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 
#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/of_platform.h>
@@ -334,7 +334,7 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) 
	struct device *dev = &pdev->dev;

	struct device_node *child, *np = dev->of_node;

	struct phy_provider *phy_provider;

	u32 version;

	u32 pllen, version;

	int ret, port = 0;



	usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
@@ -366,6 +366,19 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) 
		ret = PTR_ERR(usbphyc->rst);

		if (ret == -EPROBE_DEFER)

			goto clk_disable;



		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);

	}



	/*

	 * Wait for minimum width of powerdown pulse (ENABLE = Low):

	 * we have to ensure the PLL is disabled before phys initialization.

	 */

	if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,

				       pllen, !(pllen & PLLEN), 5, 50)) {

		dev_warn(usbphyc->dev, "PLL not reset\n");

		ret = -EPROBE_DEFER;

		goto clk_disable;

	}



	usbphyc->switch_setup = -EINVAL;