Commit 56852c62 authored by Andrew Jones's avatar Andrew Jones Committed by Anup Patel
Browse files

RISC-V: KVM: Expose Zicbom to the guest 



Guests may use the cbo.inval,clean,flush instructions when the
CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
(for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).

Add Zicbom support for KVM guests which may be enabled and
disabled from KVM userspace using the ISA extension ONE_REG API.

Also opportunistically switch the other isa extension checks in
kvm_riscv_vcpu_update_config() to riscv_isa_extension_available().

Signed-off-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent afd5dde9

arch/riscv/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_SSTC,

	KVM_RISCV_ISA_EXT_SVINVAL,

	KVM_RISCV_ISA_EXT_ZIHINTPAUSE,

	KVM_RISCV_ISA_EXT_ZICBOM,

	KVM_RISCV_ISA_EXT_MAX,

};

arch/riscv/kvm/vcpu.c

+7 −2
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ static const unsigned long kvm_isa_ext_arr[] = { 
	KVM_ISA_EXT_ARR(SVINVAL),

	KVM_ISA_EXT_ARR(SVPBMT),

	KVM_ISA_EXT_ARR(ZIHINTPAUSE),

	KVM_ISA_EXT_ARR(ZICBOM),

};



static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -799,11 +800,15 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) 
{

	u64 henvcfg = 0;



	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT))

	if (riscv_isa_extension_available(isa, SVPBMT))

		henvcfg |= ENVCFG_PBMTE;



	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC))

	if (riscv_isa_extension_available(isa, SSTC))

		henvcfg |= ENVCFG_STCE;



	if (riscv_isa_extension_available(isa, ZICBOM))

		henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);



	csr_write(CSR_HENVCFG, henvcfg);

#ifdef CONFIG_32BIT

	csr_write(CSR_HENVCFGH, henvcfg >> 32);