Commit 564499f5 authored by Jonathan Marek's avatar Jonathan Marek Committed by Rob Clark
Browse files

drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650 



See downstream's "disable_tseskip" flag.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210608172808.11803-5-jonathan@marek.ca


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 58e933e3

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+6 −4
Original line number Diff line number Diff line
@@ -844,13 +844,15 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
	/* Setting the mem pool size */

	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);



	/* Setting the primFifo thresholds default values */

	/* Setting the primFifo thresholds default values,

	 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer

	*/

	if (adreno_is_a650(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

	else if (adreno_is_a640(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);

	else

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);



	/* Set the AHB default slave response to "ERROR" */

	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);