Loading arch/arm/Kconfig +0 −5 Original line number Diff line number Diff line Loading @@ -178,11 +178,6 @@ config FIQ config ARCH_MTD_XIP bool config ARM_L1_CACHE_SHIFT_6 bool help Setting ARM L1 cache line size to 64 Bytes. config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR Loading arch/arm/mm/Kconfig +5 −0 Original line number Diff line number Diff line Loading @@ -845,6 +845,11 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. config ARM_L1_CACHE_SHIFT_6 bool help Setting ARM L1 cache line size to 64 Bytes. config ARM_L1_CACHE_SHIFT int default 6 if ARM_L1_CACHE_SHIFT_6 Loading Loading
arch/arm/Kconfig +0 −5 Original line number Diff line number Diff line Loading @@ -178,11 +178,6 @@ config FIQ config ARCH_MTD_XIP bool config ARM_L1_CACHE_SHIFT_6 bool help Setting ARM L1 cache line size to 64 Bytes. config VECTORS_BASE hex default 0xffff0000 if MMU || CPU_HIGH_VECTOR Loading
arch/arm/mm/Kconfig +5 −0 Original line number Diff line number Diff line Loading @@ -845,6 +845,11 @@ config CACHE_XSC3L2 help This option enables the L2 cache on XScale3. config ARM_L1_CACHE_SHIFT_6 bool help Setting ARM L1 cache line size to 64 Bytes. config ARM_L1_CACHE_SHIFT int default 6 if ARM_L1_CACHE_SHIFT_6 Loading