Commit 562e530f authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Force ID_AA64PFR0_EL1.GIC=1 when exposing a virtual GICv3 



Until now, we always let ID_AA64PFR0_EL1.GIC reflect the value
visible on the host, even if we were running a GICv2-enabled VM
on a GICv3+compat host.

That's fine, but we also now have the case of a host that does not
expose ID_AA64PFR0_EL1.GIC==1 despite having a vGIC. Yes, this is
confusing. Thank you M1.

Let's go back to first principles and expose ID_AA64PFR0_EL1.GIC=1
when a GICv3 is exposed to the guest. This also hides a GICv4.1
CPU interface from the guest which has no business knowing about
the v4.1 extension.

Reviewed-by: default avatarAlexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211010150910.2911495-2-maz@kernel.org
parent 9e1ff307

arch/arm64/kvm/sys_regs.c

+5 −0
Original line number Diff line number Diff line
@@ -1075,6 +1075,11 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, 
		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);

		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);

		if (irqchip_in_kernel(vcpu->kvm) &&

		    vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {

			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);

			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);

		}

		break;

	case SYS_ID_AA64PFR1_EL1:

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);