Commit 560b8030 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'timers-core-2023-02-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull timer updates from Thomas Gleixner:
 "Updates for timekeeping, timers and clockevent/source drivers:

  Core:

   - Yet another round of improvements to make the clocksource watchdog
     more robust:

       - Relax the clocksource-watchdog skew criteria to match the NTP
         criteria.

       - Temporarily skip the watchdog when high memory latencies are
         detected which can lead to false-positives.

       - Provide an option to enable TSC skew detection even on systems
         where TSC is marked as reliable.

     Sigh!

   - Initialize the restart block in the nanosleep syscalls to be
     directed to the no restart function instead of doing a partial
     setup on entry.

     This prevents an erroneous restart_syscall() invocation from
     corrupting user space data. While such a situation is clearly a
     user space bug, preventing this is a correctness issue and caters
     to the least suprise principle.

   - Ignore the hrtimer slack for realtime tasks in schedule_hrtimeout()
     to align it with the nanosleep semantics.

  Drivers:

   - The obligatory new driver bindings for Mediatek, Rockchip and
     RISC-V variants.

   - Add support for the C3STOP misfeature to the RISC-V timer to handle
     the case where the timer stops in deeper idle state.

   - Set up a static key in the RISC-V timer correctly before first use.

   - The usual small improvements and fixes all over the place"

* tag 'timers-core-2023-02-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (30 commits)
  clocksource/drivers/timer-sun4i: Add CLOCK_EVT_FEAT_DYNIRQ
  clocksource/drivers/em_sti: Mark driver as non-removable
  clocksource/drivers/sh_tmu: Mark driver as non-removable
  clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first use
  clocksource/drivers/timer-microchip-pit64b: Add delay timer
  clocksource/drivers/timer-microchip-pit64b: Select driver only on ARM
  dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx
  dt-bindings: timer: mediatek,mtk-timer: add MT8365
  clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
  clocksource/drivers/sh_cmt: Mark driver as non-removable
  clocksource/drivers/timer-microchip-pit64b: Drop obsolete dependency on COMPILE_TEST
  clocksource/drivers/riscv: Increase the clock source rating
  clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT
  dt-bindings: timer: Add bindings for the RISC-V timer device
  RISC-V: time: initialize hrtimer based broadcast clock event device
  dt-bindings: timer: rk-timer: Add rktimer for rv1126
  time/debug: Fix memory leak with using debugfs_lookup()
  clocksource: Enable TSC watchdog checking of HPET and PMTMR only when requested
  posix-timers: Use atomic64_try_cmpxchg() in __update_gt_cputime()
  clocksource: Verify HPET and PMTMR when TSC unverified
  ...
parents 056612fd ab407a19

Documentation/admin-guide/kernel-parameters.txt

+10 −0
Original line number Diff line number Diff line
@@ -6369,6 +6369,16 @@ 
			in situations with strict latency requirements (where

			interruptions from clocksource watchdog are not

			acceptable).

			[x86] recalibrate: force recalibration against a HW timer

			(HPET or PM timer) on systems whose TSC frequency was

			obtained from HW or FW using either an MSR or CPUID(0x15).

			Warn if the difference is more than 500 ppm.

			[x86] watchdog: Use TSC as the watchdog clocksource with

			which to check other HW timers (HPET or PM timer), but

			only on systems where TSC has been deemed trustworthy.

			This will be suppressed by an earlier tsc=nowatchdog and

			can be overridden by a later tsc=nowatchdog.  A console

			message will flag any such suppression or overriding.



	tsc_early_khz=  [X86] Skip early TSC calibration and use the given

			value instead. Useful when the early TSC frequency discovery

Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ Required properties: 


	For those SoCs that use CPUX

	* "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)

	* "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX)



- reg: Should contain location and length for timer register.

- clocks: Should contain system clock.

Documentation/devicetree/bindings/timer/riscv,timer.yaml

0 → 100644
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Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: RISC-V timer



maintainers:

  - Anup Patel <anup@brainfault.org>



description: |+

  RISC-V platforms always have a RISC-V timer device for the supervisor-mode

  based on the time CSR defined by the RISC-V privileged specification. The

  timer interrupts of this device are configured using the RISC-V SBI Time

  extension or the RISC-V Sstc extension.



  The clock frequency of RISC-V timer device is specified via the

  "timebase-frequency" DT property of "/cpus" DT node which is described

  in Documentation/devicetree/bindings/riscv/cpus.yaml



properties:

  compatible:

    enum:

      - riscv,timer



  interrupts-extended:

    minItems: 1

    maxItems: 4096   # Should be enough?



  riscv,timer-cannot-wake-cpu:

    type: boolean

    description:

      If present, the timer interrupt cannot wake up the CPU from one or

      more suspend/idle states.



additionalProperties: false



required:

  - compatible

  - interrupts-extended



examples:

  - |

    timer {

      compatible = "riscv,timer";

      interrupts-extended = <&cpu1intc 5>,

                            <&cpu2intc 5>,

                            <&cpu3intc 5>,

                            <&cpu4intc 5>;

    };

...

Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml

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@@ -17,6 +17,7 @@ properties: 
      - items:

          - enum:

              - rockchip,rv1108-timer

              - rockchip,rv1126-timer

              - rockchip,rk3036-timer

              - rockchip,rk3128-timer

              - rockchip,rk3188-timer

Documentation/devicetree/bindings/timer/sifive,clint.yaml

+8 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ description: 
  property of "/cpus" DT node. The "timebase-frequency" DT property is

  described in Documentation/devicetree/bindings/riscv/cpus.yaml



  T-Head C906/C910 CPU cores include an implementation of CLINT too, however

  their implementation lacks a memory-mapped MTIME register, thus not

  compatible with SiFive ones.



properties:

  compatible:

    oneOf:
@@ -29,6 +33,10 @@ properties: 
              - starfive,jh7100-clint

              - canaan,k210-clint

          - const: sifive,clint0

      - items:

          - enum:

              - allwinner,sun20i-d1-clint

          - const: thead,c900-clint

      - items:

          - const: sifive,clint0

          - const: riscv,clint0