Commit 55c6d8f8 authored by Mike Golant's avatar Mike Golant Committed by Luca Coelho
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iwlwifi: support 4-bits in MAC step value



We have a MAC component (which is inside the SoC) and it has several
different HW steps.  3 bits used to be enough but now we need 4-bits
to represent all the different steps.

Properly support 4-bits in the MAC step value by refactoring all the
current handling of the MAC step/dash.

Already from family 8000 and up the dash (bits 0-1) no longer exists
and the step (until 8000 bits 2-3) consists of the dash bits as well.

To do this remove the CSR_HW_REV_STEP and the CSR_HW_REV_DASH
macros, replace them with CSR_HW_REV_STEP_DASH and add hw_rev_step
into the trans struct.

In addition remove the CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP and
CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH macros and create a new macro
combining the 2 (this way we don't need shifting or anything else.)

Signed-off-by: default avatarMatti Gottlieb <matti.gottlieb@intel.com>
Signed-off-by: default avatarMike Golant <michael.golant@intel.com>
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20211207160459.2e81a14d1f80.Ia5287e37fb3439d805336837361f6491f958e465@changeid


Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent db66abee
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+2 −6
Original line number Diff line number Diff line
@@ -1974,12 +1974,8 @@ static void iwl_nic_config(struct iwl_op_mode *op_mode)

	/* SKU Control */
	iwl_trans_set_bits_mask(priv->trans, CSR_HW_IF_CONFIG_REG,
				CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH |
				CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP,
				(CSR_HW_REV_STEP(priv->trans->hw_rev) <<
					CSR_HW_IF_CONFIG_REG_POS_MAC_STEP) |
				(CSR_HW_REV_DASH(priv->trans->hw_rev) <<
					CSR_HW_IF_CONFIG_REG_POS_MAC_DASH));
				CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH,
				CSR_HW_REV_STEP_DASH(priv->trans->hw_rev));

	/* write radio config values to register */
	if (priv->nvm_data->radio_cfg_type <= EEPROM_RF_CONFIG_TYPE_MAX) {
+2 −2
Original line number Diff line number Diff line
@@ -880,7 +880,7 @@ iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
		dump_info->hw_type =
			cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev));
		dump_info->hw_step =
			cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
			cpu_to_le32(fwrt->trans->hw_rev_step);
		memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
		       sizeof(dump_info->fw_human_readable));
		strncpy(dump_info->dev_human_readable, fwrt->trans->name,
@@ -2099,7 +2099,7 @@ static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
	dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
	dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);

	dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev));
	dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step);

	/*
	 * Several HWs all have type == 0x42, so we'll override this value
+6 −8
Original line number Diff line number Diff line
@@ -143,8 +143,7 @@
#define CSR_FUNC_SCRATCH_INIT_VALUE		(0x01010101)

/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH	(0x00000003)
#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP	(0x0000000C)
#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH	(0x0000000F)
#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM	(0x00000080)
#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x000000C0)
#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI		(0x00000100)
@@ -287,8 +286,7 @@
#define CSR_GP_CNTRL_REG_FLAG_SW_RESET			BIT(31)

/* HW REV */
#define CSR_HW_REV_DASH(_val)          (((_val) & 0x0000003) >> 0)
#define CSR_HW_REV_STEP(_val)          (((_val) & 0x000000C) >> 2)
#define CSR_HW_REV_STEP_DASH(_val)     ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH)
#define CSR_HW_REV_TYPE(_val)          (((_val) & 0x000FFF0) >> 4)

/* HW RFID */
@@ -328,10 +326,10 @@ enum {
#define CSR_HW_REV_TYPE_7265D		(0x0000210)
#define CSR_HW_REV_TYPE_NONE		(0x00001F0)
#define CSR_HW_REV_TYPE_QNJ		(0x0000360)
#define CSR_HW_REV_TYPE_QNJ_B0		(0x0000364)
#define CSR_HW_REV_TYPE_QU_B0		(0x0000334)
#define CSR_HW_REV_TYPE_QU_C0		(0x0000338)
#define CSR_HW_REV_TYPE_QUZ		(0x0000354)
#define CSR_HW_REV_TYPE_QNJ_B0		(0x0000361)
#define CSR_HW_REV_TYPE_QU_B0		(0x0000331)
#define CSR_HW_REV_TYPE_QU_C0		(0x0000332)
#define CSR_HW_REV_TYPE_QUZ		(0x0000351)
#define CSR_HW_REV_TYPE_HR_CDB		(0x0000340)
#define CSR_HW_REV_TYPE_SO		(0x0000370)
#define CSR_HW_REV_TYPE_TY		(0x0000420)
+2 −2
Original line number Diff line number Diff line
@@ -163,8 +163,8 @@ static int iwl_request_firmware(struct iwl_drv *drv, bool first)
	char tag[8];

	if (drv->trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
	    (CSR_HW_REV_STEP(drv->trans->hw_rev) != SILICON_B_STEP &&
	     CSR_HW_REV_STEP(drv->trans->hw_rev) != SILICON_C_STEP)) {
	    (drv->trans->hw_rev_step != SILICON_B_STEP &&
	     drv->trans->hw_rev_step != SILICON_C_STEP)) {
		IWL_ERR(drv,
			"Only HW steps B and C are currently supported (0x%0x)\n",
			drv->trans->hw_rev);
+1 −1
Original line number Diff line number Diff line
@@ -1609,7 +1609,7 @@ int iwl_read_external_nvm(struct iwl_trans *trans,

		/* nvm file validation, dword_buff[2] holds the file version */
		if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
		    CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
		    trans->hw_rev_step == SILICON_C_STEP &&
		    le32_to_cpu(dword_buff[2]) < 0xE4A) {
			ret = -EFAULT;
			goto out;
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