Unverified Commit 55c36f20 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!5039 [OLK-6.6] Fix disabling memory if DVSEC CXL Range does not match a CFMWS window 

Merge Pull Request from: @kile2009 
 
backporting the patches from upstream to avoid the system hanging when validating the CXL 
 
Link:https://gitee.com/openeuler/kernel/pulls/5039

 

Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents f6a1bbf1 5eb70c7c

drivers/cxl/core/pci.c

+3 −3
Original line number Diff line number Diff line
@@ -476,9 +476,9 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 
		allowed++;

	}



	if (!allowed) {

		cxl_set_mem_enable(cxlds, 0);

		info->mem_enabled = 0;

	if (!allowed && info->mem_enabled) {

		dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n");

		return -ENXIO;

	}



	/*