Commit 55ae1b75 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update tremontx uncore and topics 

Update the topic of BTCLEAR.ANY and add additional uncore event names
as per:

https://github.com/intel/event-converter-for-linux-perf/



Signed-off-by: default avatarIan Rogers <irogers@google.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com&gt;1>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220413210503.3256922-8-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 45d97cdd

tools/perf/pmu-events/arch/x86/tremontx/other.json

+1 −12
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number of BTCLEARS.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe8",

        "EventName": "BTCLEAR.ANY",

        "PDIR_COUNTER": "na",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",

        "SampleAfterValue": "200003"

    },

    {

        "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",

        "CollectPEBSRecord": "2",

tools/perf/pmu-events/arch/x86/tremontx/pipeline.json

+12 −1
Original line number Diff line number Diff line
@@ -164,6 +164,17 @@ 
        "SampleAfterValue": "200003",

        "UMask": "0xfe"

    },

    {

        "BriefDescription": "Counts the total number of BTCLEARS.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0xe8",

        "EventName": "BTCLEAR.ANY",

        "PDIR_COUNTER": "na",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",

        "SampleAfterValue": "200003"

    },

    {

        "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",

        "CollectPEBSRecord": "2",

tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json

+22 −0
Original line number Diff line number Diff line
@@ -10,6 +10,17 @@ 
        "UMask": "0x0f",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "read requests to memory controller",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x04",

        "EventName": "UNC_M_CAS_COUNT.RD",

        "PerPkg": "1",

        "ScaleUnit": "64Bytes",

        "UMask": "0x0f",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",

        "Counter": "0,1,2,3",
@@ -21,6 +32,17 @@ 
        "UMask": "0x30",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "write requests to memory controller",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x04",

        "EventName": "UNC_M_CAS_COUNT.WR",

        "PerPkg": "1",

        "ScaleUnit": "64Bytes",

        "UMask": "0x30",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "Memory controller clock ticks",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json

+94 −0
Original line number Diff line number Diff line
@@ -19,6 +19,18 @@ 
        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x35",

        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",

        "Filter": "config1=0x40e33",

        "PerPkg": "1",

        "UMask": "0xC001FE01",

        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",

        "Counter": "0,1,2,3",
@@ -31,6 +43,18 @@ 
        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "MMIO reads",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x35",

        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",

        "Filter": "config1=0x40040e33",

        "PerPkg": "1",

        "UMask": "0xC001FE01",

        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",

        "Counter": "0,1,2,3",
@@ -43,6 +67,18 @@ 
        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "MMIO writes",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x35",

        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",

        "Filter": "config1=0x40041e33",

        "PerPkg": "1",

        "UMask": "0xC001FE01",

        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",

        "Counter": "0,1,2,3",
@@ -56,6 +92,19 @@ 
        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "Streaming stores (full cache line)",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x35",

        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",

        "Filter": "config1=0x41833",

        "PerPkg": "1",

        "ScaleUnit": "64Bytes",

        "UMask": "0xC001FE01",

        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",

        "Counter": "0,1,2,3",
@@ -69,6 +118,19 @@ 
        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "Streaming stores (partial cache line)",

        "Counter": "0,1,2,3",

        "CounterType": "PGMABLE",

        "EventCode": "0x35",

        "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",

        "Filter": "config1=0x41a33",

        "PerPkg": "1",

        "ScaleUnit": "64Bytes",

        "UMask": "0xC001FE01",

        "UMaskExt": "0xC001FE",

        "Unit": "CHA"

    },

    {

        "BriefDescription": "read requests from home agent",

        "Counter": "0,1,2,3",
@@ -105,6 +167,22 @@ 
        "UMask": "0x04",

        "Unit": "IIO"

    },

    {

        "BriefDescription": "PCI Express bandwidth reading at IIO",

        "Counter": "0,1",

        "CounterType": "PGMABLE",

        "EventCode": "0x83",

        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",

        "FCMask": "0x07",

        "Filter": "ch_mask=0x1f",

        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",

        "MetricName": "LLC_MISSES.PCIE_READ",

        "PerPkg": "1",

        "PortMask": "0x01",

        "ScaleUnit": "4Bytes",

        "UMask": "0x04",

        "Unit": "IIO"

    },

    {

        "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",

        "Counter": "0,1",
@@ -121,6 +199,22 @@ 
        "UMask": "0x01",

        "Unit": "IIO"

    },

    {

        "BriefDescription": "PCI Express bandwidth writing at IIO",

        "Counter": "0,1",

        "CounterType": "PGMABLE",

        "EventCode": "0x83",

        "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",

        "FCMask": "0x07",

        "Filter": "ch_mask=0x1f",

        "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 +UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",

        "MetricName": "LLC_MISSES.PCIE_WRITE",

        "PerPkg": "1",

        "PortMask": "0x01",

        "ScaleUnit": "4Bytes",

        "UMask": "0x01",

        "Unit": "IIO"

    },

    {

        "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",

        "Counter": "0,1",