Commit 5582f3c1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2023-02-17' of... 

Merge tag 'drm-intel-next-fixes-2023-02-17' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

drm/i915 fixes for the v6.3 merge window:
- Fix eDP+DSI dual panel systems
- Fix system suspend when fbdev isn't initialized
- Fix memory leaks in scatterlist
- Fix some MCR register annotations
- Fix documentation build warnings

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v8k0xyx4.fsf@intel.com
parents fec67d18 8038510b

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −1
Original line number Diff line number Diff line
@@ -2043,7 +2043,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	/* attach connector to encoder */

	intel_connector_attach_encoder(intel_connector, encoder);



	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);

	encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port);

	intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL);



	mutex_lock(&dev_priv->drm.mode_config.mutex);

	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);

drivers/gpu/drm/i915/display/intel_backlight.c

+31 −3
Original line number Diff line number Diff line
@@ -1431,6 +1431,30 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) 
	return 0;

}



static int cnp_num_backlight_controllers(struct drm_i915_private *i915)

{

	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)

		return 1;



	if (INTEL_PCH_TYPE(i915) >= PCH_ICP)

		return 2;



	return 1;

}



static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int controller)

{

	if (controller < 0 || controller >= cnp_num_backlight_controllers(i915))

		return false;



	if (controller == 1 &&

	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&

	    INTEL_PCH_TYPE(i915) < PCH_MTP)

		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;



	return true;

}



static int

cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)

{
@@ -1440,10 +1464,14 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) 


	/*

	 * CNP has the BXT implementation of backlight, but with only one

	 * controller. TODO: ICP has multiple controllers but we only use

	 * controller 0 for now.

	 * controller. ICP+ can have two controllers, depending on pin muxing.

	 */

	panel->backlight.controller = connector->panel.vbt.backlight.controller;

	if (!cnp_backlight_controller_is_valid(i915, panel->backlight.controller)) {

		drm_dbg_kms(&i915->drm, "Invalid backlight controller %d, assuming 0\n",

			    panel->backlight.controller);

		panel->backlight.controller = 0;

	}



	pwm_ctl = intel_de_read(i915,

				BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_bios.c

+36 −13
Original line number Diff line number Diff line
@@ -1033,6 +1033,7 @@ parse_lfp_backlight(struct drm_i915_private *i915, 
	}



	panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;

	panel->vbt.backlight.controller = 0;

	if (i915->display.vbt.version >= 191) {

		size_t exp_size;
@@ -2467,6 +2468,22 @@ static enum port dvo_port_to_port(struct drm_i915_private *i915, 
					  dvo_port);

}



static enum port

dsi_dvo_port_to_port(struct drm_i915_private *i915, u8 dvo_port)

{

	switch (dvo_port) {

	case DVO_PORT_MIPIA:

		return PORT_A;

	case DVO_PORT_MIPIC:

		if (DISPLAY_VER(i915) >= 11)

			return PORT_B;

		else

			return PORT_C;

	default:

		return PORT_NONE;

	}

}



static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate)

{

	switch (vbt_max_link_rate) {
@@ -2577,6 +2594,12 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata) 
		devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;

}



static bool

intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)

{

	return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;

}



static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata)

{

	if (!devdata || devdata->i915->display.vbt.version < 158)
@@ -2627,7 +2650,7 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata, 
{

	struct drm_i915_private *i915 = devdata->i915;

	const struct child_device_config *child = &devdata->child;

	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt;

	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;

	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;



	is_dvi = intel_bios_encoder_supports_dvi(devdata);
@@ -2635,13 +2658,14 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata, 
	is_crt = intel_bios_encoder_supports_crt(devdata);

	is_hdmi = intel_bios_encoder_supports_hdmi(devdata);

	is_edp = intel_bios_encoder_supports_edp(devdata);

	is_dsi = intel_bios_encoder_supports_dsi(devdata);



	supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);

	supports_tbt = intel_bios_encoder_supports_tbt(devdata);



	drm_dbg_kms(&i915->drm,

		    "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",

		    port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,

		    "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d DSI:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",

		    port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, is_dsi,

		    HAS_LSPCON(i915) && child->lspcon,

		    supports_typec_usb, supports_tbt,

		    devdata->dsc != NULL);
@@ -2694,6 +2718,8 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata) 
	enum port port;



	port = dvo_port_to_port(i915, child->dvo_port);

	if (port == PORT_NONE && DISPLAY_VER(i915) >= 11)

		port = dsi_dvo_port_to_port(i915, child->dvo_port);

	if (port == PORT_NONE)

		return;
@@ -3442,19 +3468,16 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *i915, 


		dvo_port = child->dvo_port;



		if (dvo_port == DVO_PORT_MIPIA ||

		    (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) ||

		    (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) {

			if (port)

				*port = dvo_port - DVO_PORT_MIPIA;

			return true;

		} else if (dvo_port == DVO_PORT_MIPIB ||

			   dvo_port == DVO_PORT_MIPIC ||

			   dvo_port == DVO_PORT_MIPID) {

		if (dsi_dvo_port_to_port(i915, dvo_port) == PORT_NONE) {

			drm_dbg_kms(&i915->drm,

				    "VBT has unsupported DSI port %c\n",

				    port_name(dvo_port - DVO_PORT_MIPIA));

			continue;

		}



		if (port)

			*port = dsi_dvo_port_to_port(i915, dvo_port);

		return true;

	}



	return false;
@@ -3539,7 +3562,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 
		if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))

			continue;



		if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {

		if (dsi_dvo_port_to_port(i915, child->dvo_port) == encoder->port) {

			if (!devdata->dsc)

				return false;

drivers/gpu/drm/i915/display/intel_fbdev.c

+7 −1
Original line number Diff line number Diff line
@@ -620,7 +620,13 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous 
	struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;

	struct fb_info *info;



	if (!ifbdev || !ifbdev->vma)

	if (!ifbdev)

		return;



	if (drm_WARN_ON(&dev_priv->drm, !HAS_DISPLAY(dev_priv)))

		return;



	if (!ifbdev->vma)

		goto set_suspend;



	info = ifbdev->helper.info;

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −6
Original line number Diff line number Diff line
@@ -686,10 +686,7 @@ 
#define GEN6_RSTCTL				_MMIO(0x9420)



#define GEN7_MISCCPCTL				_MMIO(0x9424)

#define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)



#define GEN8_MISCCPCTL				MCR_REG(0x9424)

#define   GEN8_DOP_CLOCK_GATE_ENABLE		REG_BIT(0)

#define   GEN7_DOP_CLOCK_GATE_ENABLE		REG_BIT(0)

#define   GEN12_DOP_CLOCK_GATE_RENDER_ENABLE	REG_BIT(1)

#define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)

#define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)
@@ -979,7 +976,7 @@ 
#define   GEN7_WA_FOR_GEN7_L3_CONTROL		0x3C47FF8C

#define   GEN7_L3AGDIS				(1 << 19)



#define XEHPC_LNCFMISCCFGREG0			_MMIO(0xb01c)

#define XEHPC_LNCFMISCCFGREG0			MCR_REG(0xb01c)

#define   XEHPC_HOSTCACHEEN			REG_BIT(1)

#define   XEHPC_OVRLSCCC			REG_BIT(0)
@@ -1042,7 +1039,7 @@ 
#define XEHP_L3SCQREG7				MCR_REG(0xb188)

#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)



#define XEHPC_L3SCRUB				_MMIO(0xb18c)

#define XEHPC_L3SCRUB				MCR_REG(0xb18c)

#define   SCRUB_CL_DWNGRADE_SHARED		REG_BIT(12)

#define   SCRUB_RATE_PER_BANK_MASK		REG_GENMASK(2, 0)

#define   SCRUB_RATE_4B_PER_CLK			REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)