Commit 5570ba2e authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: CPS: Prevent multi-core with dcache aliasing 



Systems using the MIPS Coherence Manager (CM) cannot support multi-core
SMP with dcache aliasing. This is because CPU caches are VIPT, but
interventions in CM-based systems provide only the physical address to
remote caches. This means that interventions may behave incorrectly in
the presence of an aliasing dcache, since the physical address used
when handling an intervention may lead to operation on an aliased cache
line rather than the correct line.

Prevent us from running into this issue by refusing to boot secondary
cores in systems where dcache aliasing may occur.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16196/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c8b7712c

arch/mips/kernel/smp-cps.c

+5 −3
Original line number Diff line number Diff line
@@ -142,9 +142,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) 


	/* Warn the user if the CCA prevents multi-core */

	ncores = mips_cm_numcores();

	if (cca_unsuitable && ncores > 1) {

		pr_warn("Using only one core due to unsuitable CCA 0x%x\n",

			cca);

	if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {

		pr_warn("Using only one core due to %s%s%s\n",

			cca_unsuitable ? "unsuitable CCA" : "",

			(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",

			cpu_has_dc_aliases ? "dcache aliasing" : "");



		for_each_present_cpu(c) {

			if (cpu_data[c].core)