Unverified Commit 5566ccc5 authored by Mark Brown's avatar Mark Brown
Browse files

spi: add new SoC mt8186 support for spi-mtk-nor 

Merge series from guochun.mao@mediatek.com <guochun.mao@mediatek.com>:

These patches is mainly for adding mt8186 support.
The spi nor controller of mt8186 has some differences,
it needs one more clk, axi_s, for dma feature.
And also needs one extra dummy bit when read flash registers.
parents 7f2a3cf4 ceab11a3

Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml

+4 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ properties: 
              - mediatek,mt7622-nor

              - mediatek,mt7623-nor

              - mediatek,mt7629-nor

              - mediatek,mt8186-nor

              - mediatek,mt8192-nor

              - mediatek,mt8195-nor

          - enum:
@@ -49,6 +50,8 @@ properties: 
      - description: clock used for controller

      - description: clock used for nor dma bus. this depends on hardware

                     design, so this is optional.

      - description: clock used for controller axi slave bus.

                     this depends on hardware design, so it is optional.



  clock-names:

    minItems: 2
@@ -56,6 +59,7 @@ properties: 
      - const: spi

      - const: sf

      - const: axi

      - const: axi_s



required:

  - compatible

drivers/spi/spi-mtk-nor.c

+61 −10
Original line number Diff line number Diff line
@@ -95,6 +95,17 @@ 


#define CLK_TO_US(sp, clkcnt)		DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)



struct mtk_nor_caps {

	u8 dma_bits;



	/* extra_dummy_bit is adding for the IP of new SoCs.

	 * Some new SoCs modify the timing of fetching registers' values

	 * and IDs of nor flash, they need a extra_dummy_bit which can add

	 * more clock cycles for fetching data.

	 */

	u8 extra_dummy_bit;

};



struct mtk_nor {

	struct spi_controller *ctlr;

	struct device *dev;
@@ -104,11 +115,13 @@ struct mtk_nor { 
	struct clk *spi_clk;

	struct clk *ctlr_clk;

	struct clk *axi_clk;

	struct clk *axi_s_clk;

	unsigned int spi_freq;

	bool wbuf_en;

	bool has_irq;

	bool high_dma;

	struct completion op_done;

	const struct mtk_nor_caps *caps;

};



static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
@@ -554,7 +567,12 @@ static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op) 
	}



	// trigger op

	if (rx_len)

		writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,

		       sp->base + MTK_NOR_REG_PRG_CNT);

	else

		writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);



	ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,

			       prg_len * BITS_PER_BYTE);

	if (ret)
@@ -674,6 +692,7 @@ static void mtk_nor_disable_clk(struct mtk_nor *sp) 
	clk_disable_unprepare(sp->spi_clk);

	clk_disable_unprepare(sp->ctlr_clk);

	clk_disable_unprepare(sp->axi_clk);

	clk_disable_unprepare(sp->axi_s_clk);

}



static int mtk_nor_enable_clk(struct mtk_nor *sp)
@@ -697,6 +716,14 @@ static int mtk_nor_enable_clk(struct mtk_nor *sp) 
		return ret;

	}



	ret = clk_prepare_enable(sp->axi_s_clk);

	if (ret) {

		clk_disable_unprepare(sp->spi_clk);

		clk_disable_unprepare(sp->ctlr_clk);

		clk_disable_unprepare(sp->axi_clk);

		return ret;

	}



	return 0;

}
@@ -743,9 +770,25 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops = { 
	.exec_op = mtk_nor_exec_op

};



const struct mtk_nor_caps mtk_nor_caps_mt8173 = {

	.dma_bits = 32,

	.extra_dummy_bit = 0,

};



const struct mtk_nor_caps mtk_nor_caps_mt8186 = {

	.dma_bits = 32,

	.extra_dummy_bit = 1,

};



const struct mtk_nor_caps mtk_nor_caps_mt8192 = {

	.dma_bits = 36,

	.extra_dummy_bit = 0,

};



static const struct of_device_id mtk_nor_match[] = {

	{ .compatible = "mediatek,mt8192-nor", .data = (void *)36 },

	{ .compatible = "mediatek,mt8173-nor", .data = (void *)32 },

	{ .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },

	{ .compatible = "mediatek,mt8186-nor", .data = &mtk_nor_caps_mt8186 },

	{ .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, mtk_nor_match);
@@ -754,10 +797,10 @@ static int mtk_nor_probe(struct platform_device *pdev) 
{

	struct spi_controller *ctlr;

	struct mtk_nor *sp;

	struct mtk_nor_caps *caps;

	void __iomem *base;

	struct clk *spi_clk, *ctlr_clk, *axi_clk;

	struct clk *spi_clk, *ctlr_clk, *axi_clk, *axi_s_clk;

	int ret, irq;

	unsigned long dma_bits;



	base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(base))
@@ -775,10 +818,16 @@ static int mtk_nor_probe(struct platform_device *pdev) 
	if (IS_ERR(axi_clk))

		return PTR_ERR(axi_clk);



	dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);

	if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {

		dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);

		return -EINVAL;

	axi_s_clk = devm_clk_get_optional(&pdev->dev, "axi_s");

	if (IS_ERR(axi_s_clk))

		return PTR_ERR(axi_s_clk);



	caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);



	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));

	if (ret) {

		dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits);

		return ret;

	}



	ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
@@ -808,7 +857,9 @@ static int mtk_nor_probe(struct platform_device *pdev) 
	sp->spi_clk = spi_clk;

	sp->ctlr_clk = ctlr_clk;

	sp->axi_clk = axi_clk;

	sp->high_dma = (dma_bits > 32);

	sp->axi_s_clk = axi_s_clk;

	sp->caps = caps;

	sp->high_dma = caps->dma_bits > 32;

	sp->buffer = dmam_alloc_coherent(&pdev->dev,

				MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,

				&sp->buffer_dma, GFP_KERNEL);