Commit 555904d0 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: MM_SLICE is not needed anymore 



As the 8xx now manages 512k pages in standard page tables,
it doesn't need CONFIG_PPC_MM_SLICES anymore.

Don't select it anymore and remove all related code.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/98e8ccd424476ea73cced2b89ba38eb2ed8144fb.1589866984.git.christophe.leroy@csgroup.eu
parent d4870b89

arch/powerpc/include/asm/nohash/32/mmu-8xx.h

+0 −64
Original line number Diff line number Diff line
@@ -176,12 +176,6 @@ 
 */

#define SPRN_M_TW	799



#ifdef CONFIG_PPC_MM_SLICES

#include <asm/nohash/32/slice.h>

#define SLICE_ARRAY_SIZE	(1 << (32 - SLICE_LOW_SHIFT - 1))

#define LOW_SLICE_ARRAY_SZ	SLICE_ARRAY_SIZE

#endif



#if defined(CONFIG_PPC_4K_PAGES)

#define mmu_virtual_psize	MMU_PAGE_4K

#elif defined(CONFIG_PPC_16K_PAGES)
@@ -199,71 +193,13 @@ 


#include <linux/mmdebug.h>



struct slice_mask {

	u64 low_slices;

	DECLARE_BITMAP(high_slices, 0);

};



typedef struct {

	unsigned int id;

	unsigned int active;

	unsigned long vdso_base;

#ifdef CONFIG_PPC_MM_SLICES

	u16 user_psize;		/* page size index */

	unsigned char low_slices_psize[SLICE_ARRAY_SIZE];

	unsigned char high_slices_psize[0];

	unsigned long slb_addr_limit;

	struct slice_mask mask_base_psize; /* 4k or 16k */

	struct slice_mask mask_512k;

	struct slice_mask mask_8m;

#endif

	void *pte_frag;

} mm_context_t;



#ifdef CONFIG_PPC_MM_SLICES

static inline u16 mm_ctx_user_psize(mm_context_t *ctx)

{

	return ctx->user_psize;

}



static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)

{

	ctx->user_psize = user_psize;

}



static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)

{

	return ctx->low_slices_psize;

}



static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)

{

	return ctx->high_slices_psize;

}



static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)

{

	return ctx->slb_addr_limit;

}



static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)

{

	ctx->slb_addr_limit = limit;

}



static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)

{

	if (psize == MMU_PAGE_512K)

		return &ctx->mask_512k;

	if (psize == MMU_PAGE_8M)

		return &ctx->mask_8m;



	BUG_ON(psize != mmu_virtual_psize);



	return &ctx->mask_base_psize;

}

#endif /* CONFIG_PPC_MM_SLICE */



#define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)

#define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))

arch/powerpc/include/asm/nohash/32/slice.h

deleted100644 → 0
+0 −20
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_POWERPC_NOHASH_32_SLICE_H

#define _ASM_POWERPC_NOHASH_32_SLICE_H



#ifdef CONFIG_PPC_MM_SLICES



#define SLICE_LOW_SHIFT		26	/* 64 slices */

#define SLICE_LOW_TOP		(0x100000000ull)

#define SLICE_NUM_LOW		(SLICE_LOW_TOP >> SLICE_LOW_SHIFT)

#define GET_LOW_SLICE_INDEX(addr)	((addr) >> SLICE_LOW_SHIFT)



#define SLICE_HIGH_SHIFT	0

#define SLICE_NUM_HIGH		0ul

#define GET_HIGH_SLICE_INDEX(addr)	(addr & 0)



#define SLB_ADDR_LIMIT_DEFAULT	DEFAULT_MAP_WINDOW



#endif /* CONFIG_PPC_MM_SLICES */



#endif /* _ASM_POWERPC_NOHASH_32_SLICE_H */

arch/powerpc/include/asm/slice.h

+0 −2
Original line number Diff line number Diff line
@@ -4,8 +4,6 @@ 


#ifdef CONFIG_PPC_BOOK3S_64

#include <asm/book3s/64/slice.h>

#elif defined(CONFIG_PPC_MMU_NOHASH_32)

#include <asm/nohash/32/slice.h>

#endif



#ifndef __ASSEMBLY__

arch/powerpc/platforms/Kconfig.cputype

+0 −1
Original line number Diff line number Diff line
@@ -55,7 +55,6 @@ config PPC_8xx 
	select SYS_SUPPORTS_HUGETLBFS

	select PPC_HAVE_KUEP

	select PPC_HAVE_KUAP

	select PPC_MM_SLICES if HUGETLB_PAGE

	select HAVE_ARCH_VMAP_STACK



config 40x