Commit 551c8185 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-misc-fixes' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes 



(I've pulled from a non-tag to get the ttm regression fix)
drm-misc-fixes-2021-02-10:
 * dp_mst: Don't report un-attached ports as connected
 * sun4i: tcon1 sync polarity fix; Always set HDMI clock rate; Fix
          H6 HDMI PHY config; Fix H6 max frequency
 * vc4: Fix buffer overflow
 * xlnx: Fix memory leak
 * ttm: page pool regression fix.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/YCPo6g3gDxD3P//h@linux-uq9g
parents 0594bc74 811ee9df

drivers/gpu/drm/drm_dp_mst_topology.c

+1 −0
Original line number Diff line number Diff line
@@ -4224,6 +4224,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector, 


	switch (port->pdt) {

	case DP_PEER_DEVICE_NONE:

		break;

	case DP_PEER_DEVICE_MST_BRANCHING:

		if (!port->mcs)

			ret = connector_status_connected;

drivers/gpu/drm/sun4i/sun4i_tcon.c

+25 −0
Original line number Diff line number Diff line
@@ -689,6 +689,30 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 
		     SUN4I_TCON1_BASIC5_V_SYNC(vsync) |

		     SUN4I_TCON1_BASIC5_H_SYNC(hsync));



	/* Setup the polarity of multiple signals */

	if (tcon->quirks->polarity_in_ch0) {

		val = 0;



		if (mode->flags & DRM_MODE_FLAG_PHSYNC)

			val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;



		if (mode->flags & DRM_MODE_FLAG_PVSYNC)

			val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;



		regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);

	} else {

		/* according to vendor driver, this bit must be always set */

		val = SUN4I_TCON1_IO_POL_UNKNOWN;



		if (mode->flags & DRM_MODE_FLAG_PHSYNC)

			val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;



		if (mode->flags & DRM_MODE_FLAG_PVSYNC)

			val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;



		regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);

	}



	/* Map output pins to channel 1 */

	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,

			   SUN4I_TCON_GCTL_IOMAP_MASK,
@@ -1517,6 +1541,7 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 


static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {

	.has_channel_1		= true,

	.polarity_in_ch0	= true,

	.set_mux		= sun8i_r40_tcon_tv_set_mux,

};

drivers/gpu/drm/sun4i/sun4i_tcon.h

+6 −0
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ 
#define SUN4I_TCON1_BASIC5_V_SYNC(height)		(((height) - 1) & 0x3ff)



#define SUN4I_TCON1_IO_POL_REG			0xf0

/* there is no documentation about this bit */

#define SUN4I_TCON1_IO_POL_UNKNOWN			BIT(26)

#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE		BIT(25)

#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE		BIT(24)



#define SUN4I_TCON1_IO_TRI_REG			0xf4



#define SUN4I_TCON_ECC_FIFO_REG			0xf8
@@ -235,6 +240,7 @@ struct sun4i_tcon_quirks { 
	bool	needs_de_be_mux; /* sun6i needs mux to select backend */

	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */

	bool	supports_lvds;   /* Does the TCON support an LVDS output? */

	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */

	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */



	/* callback to handle tcon muxing options */

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

+3 −7
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder, 
{

	struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);



	if (hdmi->quirks->set_rate)

	clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);

}
@@ -48,11 +47,9 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, 
{

	/*

	 * Controller support maximum of 594 MHz, which correlates to

	 * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than

	 * 340 MHz scrambling has to be enabled. Because scrambling is

	 * not yet implemented, just limit to 340 MHz for now.

	 * 4K@60Hz 4:4:4 or RGB.

	 */

	if (mode->clock > 340000)

	if (mode->clock > 594000)

		return MODE_CLOCK_HIGH;



	return MODE_OK;
@@ -295,7 +292,6 @@ static int sun8i_dw_hdmi_remove(struct platform_device *pdev) 


static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {

	.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,

	.set_rate = true,

};



static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

+0 −1
Original line number Diff line number Diff line
@@ -179,7 +179,6 @@ struct sun8i_dw_hdmi_quirks { 
	enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,

					   const struct drm_display_info *info,

					   const struct drm_display_mode *mode);

	unsigned int set_rate : 1;

	unsigned int use_drm_infoframe : 1;

};