Commit 54e9ea3d authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher
Browse files

drm/amd/display: Fix DCN2.1 default DSC clocks 



[WHY]
Low dscclk in high vlevels blocks some DSC modes.

[HOW]
Update dscclk to 1/3 of dispclk.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 39173f24

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+3 −3
Original line number Diff line number Diff line
@@ -565,7 +565,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 
				.dppclk_mhz = 847.06,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 953.0,

				.dscclk_mhz = 489.0,

				.dscclk_mhz = 300.0,

				.dram_speed_mts = 2400.0,

			},

			{
@@ -576,7 +576,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 
				.dppclk_mhz = 960.00,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 278.0,

				.dscclk_mhz = 287.67,

				.dscclk_mhz = 342.86,

				.dram_speed_mts = 2666.0,

			},

			{
@@ -587,7 +587,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 
				.dppclk_mhz = 1028.57,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 715.0,

				.dscclk_mhz = 318.334,

				.dscclk_mhz = 369.23,

				.dram_speed_mts = 3200.0,

			},

			{