Commit 54af0ceb authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes 



Add device nodes required to enable GPU on the SM8350 platform.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Workaround for lacking RPMH_REGULATOR_LEVEL_LOW_SVS_L1 constant]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230209133839.762631-6-dmitry.baryshkov@linaro.org
parent 51f83fbb

arch/arm64/boot/dts/qcom/sm8350.dtsi

+178 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,dispcc-sm8350.h>

#include <dt-bindings/clock/qcom,gcc-sm8350.h>

#include <dt-bindings/clock/qcom,gpucc-sm8350.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/dma/qcom-gpi.h>

#include <dt-bindings/gpio/gpio.h>
@@ -1765,6 +1766,183 @@ 
			#hwlock-cells = <1>;

		};



		gpu: gpu@3d00000 {

			compatible = "qcom,adreno-660.1", "qcom,adreno";



			reg = <0 0x03d00000 0 0x40000>,

			      <0 0x03d9e000 0 0x1000>,

			      <0 0x03d61000 0 0x800>;

			reg-names = "kgsl_3d0_reg_memory",

				    "cx_mem",

				    "cx_dbgc";



			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;



			iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;



			operating-points-v2 = <&gpu_opp_table>;



			qcom,gmu = <&gmu>;



			status = "disabled";



			zap-shader {

				memory-region = <&pil_gpu_mem>;

			};



			/* note: downstream checks gpu binning for 670 Mhz */

			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-840000000 {

					opp-hz = /bits/ 64 <840000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

				};



				opp-778000000 {

					opp-hz = /bits/ 64 <778000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

				};



				opp-738000000 {

					opp-hz = /bits/ 64 <738000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				};



				opp-676000000 {

					opp-hz = /bits/ 64 <676000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

				};



				opp-608000000 {

					opp-hz = /bits/ 64 <608000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;

				};



				opp-540000000 {

					opp-hz = /bits/ 64 <540000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				};



				opp-491000000 {

					opp-hz = /bits/ 64 <491000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;

				};



				opp-443000000 {

					opp-hz = /bits/ 64 <443000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

				};



				opp-379000000 {

					opp-hz = /bits/ 64 <379000000>;

					opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;

				};



				opp-315000000 {

					opp-hz = /bits/ 64 <315000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

				};

			};

		};



		gmu: gmu@3d6a000 {

			compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";



			reg = <0 0x03d6a000 0 0x34000>,

			      <0 0x03de0000 0 0x10000>,

			      <0 0x0b290000 0 0x10000>;

			reg-names = "gmu", "rscc", "gmu_pdc";



			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hfi", "gmu";



			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_CXO_CLK>,

				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gpucc GPU_CC_AHB_CLK>,

				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

			clock-names = "gmu",

				      "cxo",

				      "axi",

				      "memnoc",

				      "ahb",

				      "hub",

				      "smmu_vote";



			power-domains = <&gpucc GPU_CX_GDSC>,

					<&gpucc GPU_GX_GDSC>;

			power-domain-names = "cx",

					     "gx";



			iommus = <&adreno_smmu 5 0x400>;



			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				};

			};

		};



		gpucc: clock-controller@3d90000 {

			compatible = "qcom,sm8350-gpucc";

			reg = <0 0x03d90000 0 0x9000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			clock-names = "bi_tcxo",

				      "gcc_gpu_gpll0_clk_src",

				      "gcc_gpu_gpll0_div_clk_src";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		adreno_smmu: iommu@3da0000 {

			compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";

			reg = <0 0x03da0000 0 0x20000>;

			#iommu-cells = <2>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

				 <&gpucc GPU_CC_AHB_CLK>,

				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,

				 <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,

				 <&gpucc GPU_CC_HUB_AON_CLK>;

			clock-names = "bus",

				      "iface",

				      "ahb",

				      "hlos1_vote_gpu_smmu",

				      "cx_gmu",

				      "hub_cx_int",

				      "hub_aon";



			power-domains = <&gpucc GPU_CX_GDSC>;

			dma-coherent;

		};



		lpass_ag_noc: interconnect@3c40000 {

			compatible = "qcom,sm8350-lpass-ag-noc";

			reg = <0 0x03c40000 0 0xf080>;