Commit 54838a4f authored by Zeng Guang's avatar Zeng Guang Committed by Jason Zeng
Browse files

KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode 

mainline inclusion
from mainline-v6.0-rc1
commit 5413bcba
category: feature
feature: IPI Virtualization
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5ODSC
CVE: N/A
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5413bcba7ed57206178d60ee03dd5bb3a460e645



Intel-SIG: commit 5413bcba ("KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode")

-------------------------------------

KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode

Upcoming Intel CPUs will support virtual x2APIC MSR writes to the vICR,
i.e. will trap and generate an APIC-write VM-Exit instead of intercepting
the WRMSR.  Add support for handling "nodecode" x2APIC writes, which
were previously impossible.

Note, x2APIC MSR writes are 64 bits wide.

Signed-off-by: default avatarZeng Guang <guang.zeng@intel.com>
Message-Id: <20220419153516.11739-1-guang.zeng@intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarJason Zeng <jason.zeng@intel.com>
parent 88642907

arch/x86/kvm/lapic.c

+9 −3
Original line number Diff line number Diff line
@@ -2174,15 +2174,21 @@ EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); 
/* emulate APIC access in a trap manner */

void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)

{

	u32 val = 0;

	struct kvm_lapic *apic = vcpu->arch.apic;

	u64 val = 0;



	/* hw has done the conditional check and inst decode */

	offset &= 0xff0;



	kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);

	/* exception dealing with 64bit data on vICR in x2apic mode */

	if ((offset == APIC_ICR) && apic_x2apic_mode(apic)) {

		val = kvm_lapic_get_reg64(apic, offset);

		kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(val>>32));

	} else

		kvm_lapic_reg_read(apic, offset, 4, &val);



	/* TODO: optimize to just emulate side effect w/o one more write */

	kvm_lapic_reg_write(vcpu->arch.apic, offset, val);

	kvm_lapic_reg_write(apic, offset, (u32)val);

}

EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);

arch/x86/kvm/lapic.h

+5 −0
Original line number Diff line number Diff line
@@ -162,6 +162,11 @@ static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 
	return *((u32 *) (apic->regs + reg_off));

}



static inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg_off)

{

	return *((u64 *) (apic->regs + reg_off));

}



static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)

{

	*((u32 *) (regs + reg_off)) = val;