Commit 547cc9be authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf_urgent_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Borislav Petkov:

 - Drop the __weak attribute from a function prototype as it otherwise
   leads to the function getting replaced by a dummy stub

 - Fix the umask value setup of the frontend event as former is
   different on two Intel cores

* tag 'perf_urgent_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL
  perf/core: Drop __weak attribute from arch_perf_update_userpage() prototype
parents 300edd75 a6742cb9

arch/x86/events/intel/core.c

+14 −1
Original line number Diff line number Diff line
@@ -349,6 +349,16 @@ static struct event_constraint intel_spr_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {

	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),

	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),

	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),

	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),

	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),

	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),

	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),

	EVENT_EXTRA_END

};



EVENT_ATTR_STR(mem-loads,	mem_ld_nhm,	"event=0x0b,umask=0x10,ldlat=3");

EVENT_ATTR_STR(mem-loads,	mem_ld_snb,	"event=0xcd,umask=0x1,ldlat=3");
@@ -6496,6 +6506,7 @@ __init int intel_pmu_init(void) 
	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		fallthrough;

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:
@@ -6506,7 +6517,8 @@ __init int intel_pmu_init(void) 


		x86_pmu.event_constraints = intel_spr_event_constraints;

		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_gnr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_ept = 1;

		x86_pmu.pebs_aliases = NULL;
@@ -6650,6 +6662,7 @@ __init int intel_pmu_init(void) 
		pmu->pebs_constraints = intel_grt_pebs_event_constraints;

		pmu->extra_regs = intel_grt_extra_regs;

		if (is_mtl(boot_cpu_data.x86_model)) {

			x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs;

			x86_pmu.pebs_latency_data = mtl_latency_data_small;

			extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?

				mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;

include/linux/perf_event.h

+3 −3
Original line number Diff line number Diff line
@@ -1845,7 +1845,7 @@ int perf_event_exit_cpu(unsigned int cpu); 
#define perf_event_exit_cpu	NULL

#endif



extern void __weak arch_perf_update_userpage(struct perf_event *event,

extern void arch_perf_update_userpage(struct perf_event *event,

				      struct perf_event_mmap_page *userpg,

				      u64 now);