Commit 544021e3 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Maarten Lankhorst
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drm/i915/jsl: Add W/A 1409054076 for JSL 



When pipe A is disabled and MIPI DSI is enabled on pipe B,
the AMT KVMR feature will incorrectly see pipe A as enabled.
Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
it set while DSI is enabled on pipe B. No impact to setting
it all the time.

Changes since V5:
	- Added reviewed-by
	- Removed redundant braces and debug message format - Imre
Changes since V4:
        - Modified function comment Wa_<number>:icl,jsl,ehl - Lucas
        - Modified debug message in sync state - Imre
Changes since V3:
        - More meaningful name to workaround - Imre
        - Remove boolean check clear flag
        - Add WA_verify hook in dsi sync_state
Changes since V2:
        - Used REG_BIT, ignored pipe A and used sw state check - Jani
        - Made function wrapper - Jani
Changes since V1:
        - ./dim checkpatch errors addressed

Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210615105613.851491-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent b91e3c83

drivers/gpu/drm/i915/display/icl_dsi.c

+42 −0
Original line number Diff line number Diff line
@@ -1253,15 +1253,36 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 
	gen11_dsi_set_transcoder_timings(encoder, pipe_config);

}



/*

 * Wa_1409054076:icl,jsl,ehl

 * When pipe A is disabled and MIPI DSI is enabled on pipe B,

 * the AMT KVMR feature will incorrectly see pipe A as enabled.

 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave

 * it set while DSI is enabled on pipe B

 */

static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,

				     enum pipe pipe, bool enable)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)

		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

			     IGNORE_KVMR_PIPE_A,

			     enable ? IGNORE_KVMR_PIPE_A : 0);

}

static void gen11_dsi_enable(struct intel_atomic_state *state,

			     struct intel_encoder *encoder,

			     const struct intel_crtc_state *crtc_state,

			     const struct drm_connector_state *conn_state)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);



	drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);



	/* Wa_1409054076:icl,jsl,ehl */

	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);



	/* step6d: enable dsi transcoder */

	gen11_dsi_enable_transcoder(encoder);
@@ -1415,6 +1436,7 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, 
			      const struct drm_connector_state *old_conn_state)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);



	/* step1: turn off backlight */

	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
@@ -1423,6 +1445,9 @@ static void gen11_dsi_disable(struct intel_atomic_state *state, 
	/* step2d,e: disable transcoder and wait */

	gen11_dsi_disable_transcoder(encoder);



	/* Wa_1409054076:icl,jsl,ehl */

	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);



	/* step2f,g: powerdown panel */

	gen11_dsi_powerdown_panel(encoder);
@@ -1548,6 +1573,22 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, 
		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;

}



static void gen11_dsi_sync_state(struct intel_encoder *encoder,

				 const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);

	enum pipe pipe = intel_crtc->pipe;



	/* wa verify 1409054076:icl,jsl,ehl */

	if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&

	    !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

		drm_dbg_kms(&dev_priv->drm,

			    "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",

			    encoder->base.base.id,

			    encoder->base.name);

}



static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,

					struct intel_crtc_state *crtc_state)

{
@@ -1966,6 +2007,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	encoder->post_disable = gen11_dsi_post_disable;

	encoder->port = port;

	encoder->get_config = gen11_dsi_get_config;

	encoder->sync_state = gen11_dsi_sync_state;

	encoder->update_pipe = intel_panel_update_backlight;

	encoder->compute_config = gen11_dsi_compute_config;

	encoder->get_hw_state = gen11_dsi_get_hw_state;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -8095,6 +8095,7 @@ enum { 
# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)



#define CHICKEN_PAR1_1			_MMIO(0x42080)

#define  IGNORE_KVMR_PIPE_A		REG_BIT(23)

#define  KBL_ARB_FILL_SPARE_22		REG_BIT(22)

#define  DIS_RAM_BYPASS_PSR2_MAN_TRACK	(1 << 16)

#define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)