Commit 54203417 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "I think we have a bit less than usual on the architecture side, but
  that's somewhat balanced out by a large crop of perf/PMU driver
  updates and extensions to our selftests.

  CPU features and system registers:

   - Advertise hinted conditional branch support (FEAT_HBC) to userspace

   - Avoid false positive "SANITY CHECK" warning when xCR registers
     differ outside of the length field

  Documentation:

   - Fix macro name typo in SME documentation

  Entry code:

   - Unmask exceptions earlier on the system call entry path

  Memory management:

   - Don't bother clearing PTE_RDONLY for dirty ptes in pte_wrprotect()
     and pte_modify()

  Perf and PMU drivers:

   - Initial support for Coresight TRBE devices on ACPI systems (the
     coresight driver changes will come later)

   - Fix hw_breakpoint single-stepping when called from bpf

   - Fixes for DDR PMU on i.MX8MP SoC

   - Add NUMA-awareness to Hisilicon PCIe PMU driver

   - Fix locking dependency issue in Arm DMC620 PMU driver

   - Workaround Hisilicon erratum 162001900 in the SMMUv3 PMU driver

   - Add support for Arm CMN-700 r3 parts to the CMN PMU driver

   - Add support for recent Arm Cortex CPU PMUs

   - Update Hisilicon PMU maintainers

  Selftests:

   - Add a bunch of new features to the hwcap test (JSCVT, PMULL, AES,
     SHA1, etc)

   - Fix SSVE test to leave streaming-mode after grabbing the signal
     context

   - Add new test for SVE vector-length changes with SME enabled

  Miscellaneous:

   - Allow compiler to warn on suspicious looking system register
     expressions

   - Work around SDEI firmware bug by aborting any running handlers on a
     kernel crash

   - Fix some harmless warnings when building with W=1

   - Remove some unused function declarations

   - Other minor fixes and cleanup"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (62 commits)
  drivers/perf: hisi: Update HiSilicon PMU maintainers
  arm_pmu: acpi: Add a representative platform device for TRBE
  arm_pmu: acpi: Refactor arm_spe_acpi_register_device()
  kselftest/arm64: Fix hwcaps selftest build
  hw_breakpoint: fix single-stepping when using bpf_overflow_handler
  arm64/sysreg: refactor deprecated strncpy
  kselftest/arm64: add jscvt feature to hwcap test
  kselftest/arm64: add pmull feature to hwcap test
  kselftest/arm64: add AES feature check to hwcap test
  kselftest/arm64: add SHA1 and related features to hwcap test
  arm64: sysreg: Generate C compiler warnings on {read,write}_sysreg_s arguments
  kselftest/arm64: build BTI tests in output directory
  perf/imx_ddr: don't enable counter0 if none of 4 counters are used
  perf/imx_ddr: speed up overflow frequency of cycle
  drivers/perf: hisi: Schedule perf session according to locality
  kselftest/arm64: fix a memleak in zt_regs_run()
  perf/arm-dmc620: Fix dmc620_pmu_irqs_lock/cpu_hotplug_lock circular lock dependency
  perf/smmuv3: Add MODULE_ALIAS for module auto loading
  perf/smmuv3: Enable HiSilicon Erratum 162001900 quirk for HIP08/09
  kselftest/arm64: Size sycall-abi buffers for the actual maximum VL
  ...
parents bb2d9e54 e1df2721

Documentation/arch/arm64/silicon-errata.rst

+11 −8
Original line number Diff line number Diff line
@@ -63,6 +63,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #1902691        | ARM64_ERRATUM_1902691       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2051678        | ARM64_ERRATUM_2051678       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2658417        | ARM64_ERRATUM_2658417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |
@@ -109,14 +117,6 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2051678        | ARM64_ERRATUM_2051678       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2658417        | ARM64_ERRATUM_2658417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |
@@ -198,6 +198,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip08 SMMU PMCG | #162001800      | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | Hip08 SMMU PMCG | #162001900      | N/A                         |

|                | Hip09 SMMU PMCG |                 |                             |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

Documentation/arch/arm64/sme.rst

+1 −1
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ The regset data starts with struct user_za_header, containing: 
  VL is supported.



* The size and layout of the payload depends on the header fields.  The

  SME_PT_ZA_*() macros are provided to facilitate access to the data.

  ZA_PT_ZA*() macros are provided to facilitate access to the data.



* In either case, for SETREGSET it is permissible to omit the payload, in which

  case the vector length and flags are changed and PSTATE.ZA is set to 0

Documentation/devicetree/bindings/arm/pmu.yaml

+5 −0
Original line number Diff line number Diff line
@@ -49,9 +49,14 @@ properties: 
          - arm,cortex-a77-pmu

          - arm,cortex-a78-pmu

          - arm,cortex-a510-pmu

          - arm,cortex-a520-pmu

          - arm,cortex-a710-pmu

          - arm,cortex-a715-pmu

          - arm,cortex-a720-pmu

          - arm,cortex-x1-pmu

          - arm,cortex-x2-pmu

          - arm,cortex-x3-pmu

          - arm,cortex-x4-pmu

          - arm,neoverse-e1-pmu

          - arm,neoverse-n1-pmu

          - arm,neoverse-n2-pmu

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -9306,7 +9306,7 @@ F: drivers/crypto/hisilicon/hpre/hpre_crypto.c 
F:	drivers/crypto/hisilicon/hpre/hpre_main.c









HISILICON HNS3 PMU DRIVER









M:	Guangbin Huang <huangguangbin2@huawei.com>









M:	Jijie Shao <shaojijie@huawei.com>









S:	Supported









F:	Documentation/admin-guide/perf/hns3-pmu.rst









F:	drivers/perf/hisilicon/hns3_pmu.c








@@ -9344,7 +9344,7 @@ F:	Documentation/devicetree/bindings/net/hisilicon*.txt







F:	drivers/net/ethernet/hisilicon/

















HISILICON PMU DRIVER









M:	Shaokun Zhang <zhangshaokun@hisilicon.com>









M:	Yicong Yang <yangyicong@hisilicon.com>









M:	Jonathan Cameron <jonathan.cameron@huawei.com>









S:	Supported









W:	http://www.hisilicon.com
































arch/arm/kernel/hw_breakpoint.c



+4
−4






























Original line number
Diff line number
Diff line







@@ -626,7 +626,7 @@ int hw_breakpoint_arch_parse(struct perf_event *bp,







	hw->address &= ~alignment_mask;









	hw->ctrl.len <<= offset;



















	if (is_default_overflow_handler(bp)) {









	if (uses_default_overflow_handler(bp)) {









		/*









		 * Mismatch breakpoints are required for single-stepping









		 * breakpoints.








@@ -798,7 +798,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,







		 * Otherwise, insert a temporary mismatch breakpoint so that









		 * we can single-step over the watchpoint trigger.









		 */









		if (!is_default_overflow_handler(wp))









		if (!uses_default_overflow_handler(wp))









			continue;









step:









		enable_single_step(wp, instruction_pointer(regs));








@@ -811,7 +811,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,







		info->trigger = addr;









		pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);









		perf_bp_event(wp, regs);









		if (is_default_overflow_handler(wp))









		if (uses_default_overflow_handler(wp))









			enable_single_step(wp, instruction_pointer(regs));









	}


















@@ -886,7 +886,7 @@ static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)







			info->trigger = addr;









			pr_debug("breakpoint fired: address = 0x%x\n", addr);









			perf_bp_event(bp, regs);









			if (is_default_overflow_handler(bp))









			if (uses_default_overflow_handler(bp))









				enable_single_step(bp, addr);









			goto unlock;









		}