Commit 53fa1bff authored Jan 23, 2022 by Ben Widawsky Committed by Dan Williams Feb 08, 2022

cxl/core: Track port depth

In preparation for proving CXL subsystem usage of the device_lock()
order track the depth of ports with the expectation that shallower port
locks can be held over deeper port locks.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com

Signed-off-by: Dan Williams <dan.j.williams@intel.com>

parent d2b61ed2

drivers/cxl/core/port.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -362,6 +362,8 @@ struct cxl_port devm_cxl_add_port(struct device host, struct device *uport,
		if (IS_ERR(port))
		return port;

		if (parent_port)
		port->depth = parent_port->depth + 1;
		dev = &port->dev;
		if (parent_port)
		rc = dev_set_name(dev, "port%d", port->id);

drivers/cxl/cxl.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -252,6 +252,7 @@ struct cxl_walk_context {
		* @dports: cxl_dport instances referenced by decoders
		* @decoder_ida: allocator for decoder ids
		* @component_reg_phys: component register capability base address (optional)
		* @depth: How deep this port is relative to the root. depth 0 is the root.
		*/
		struct cxl_port {
		struct device dev;
		@@ -260,6 +261,7 @@ struct cxl_port {
		struct list_head dports;
		struct ida decoder_ida;
		resource_size_t component_reg_phys;
		unsigned int depth;
		};

		/**