Commit 53af98c0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9: switch to golden tsc registers for renoir+ 



Renoir and newer gfx9 APUs have new TSC register that is
not part of the gfxoff tile, so it can be read without
needing to disable gfx off.

Acked-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 244ee398

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+35 −11
Original line number Diff line number Diff line
@@ -140,6 +140,11 @@ MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 
#define mmTCP_CHAN_STEER_5_ARCT								0x0b0c

#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0



#define mmGOLDEN_TSC_COUNT_UPPER_Renoir                0x0025

#define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026

#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1



enum ta_ras_gfx_subblock {

	/*CPC*/

	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@@ -4238,8 +4243,25 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 


static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)

{

	uint64_t clock;

	uint64_t clock, clock_lo, clock_hi, hi_check;



	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 3, 0):

		preempt_disable();

		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);

		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);

		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);

		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over

		 * roughly every 42 seconds.

		 */

		if (hi_check != clock_hi) {

			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);

			clock_hi = hi_check;

		}

		preempt_enable();

		clock = clock_lo | (clock_hi << 32ULL);

		break;

	default:

		amdgpu_gfx_off_ctrl(adev, false);

		mutex_lock(&adev->gfx.gpu_clock_mutex);

		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
@@ -4251,6 +4273,8 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 
		}

		mutex_unlock(&adev->gfx.gpu_clock_mutex);

		amdgpu_gfx_off_ctrl(adev, true);

		break;

	}

	return clock;

}