Unverified Commit 53a09635 authored by Lars Povlsen's avatar Lars Povlsen Committed by Mark Brown
Browse files

spi: dw: Add Microchip Sparx5 support 



This adds SPI support for the Sparx5 SoC, which is using the MMIO
Designware SPI controller.

The Sparx5 differs from the Ocelot version in these areas:

 * The CS override is controlled by a new set of registers for
   this purpose.

 * The Sparx5 SPI controller has the RX sample delay register, and it
   must be configured for the (SPI NAND) device on SPI2.

 * The Sparx5 SPI controller has 2 different SPI bus interfaces on the
   same controller (don't ask...). The "spi-mux" driver should be used
   in conjunction with the SPI driver to select the appropriate bus.

Signed-off-by: default avatarLars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-3-lars.povlsen@microchip.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent bac70b54

drivers/spi/spi-dw-mmio.c

+69 −1
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ struct dw_spi_mmio { 
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE	BIT(13)

#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)	(x << 5)



#define SPARX5_FORCE_ENA			0xa4

#define SPARX5_FORCE_VAL			0xa8



/*

 * For Keem Bay, CTRLR0[31] is used to select controller mode.

 * 0: SSI is slave
@@ -54,7 +57,7 @@ struct dw_spi_mmio { 


struct dw_spi_mscc {

	struct regmap       *syscon;

	void __iomem        *spi_mst;

	void __iomem        *spi_mst; /* Not sparx5 */

};



/*
@@ -134,6 +137,70 @@ static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, 
				JAGUAR2_IF_SI_OWNER_OFFSET);

}



/*

 * The Designware SPI controller (referred to as master in the

 * documentation) automatically deasserts chip select when the tx fifo

 * is empty. The chip selects then needs to be driven by a CS override

 * register. enable is an active low signal.

 */

static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)

{

	struct dw_spi *dws = spi_master_get_devdata(spi->master);

	struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);

	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;

	u8 cs = spi->chip_select;



	if (!enable) {

		/* CS override drive enable */

		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);

		/* Now set CSx enabled */

		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));

		/* Allow settle */

		usleep_range(1, 5);

	} else {

		/* CS value */

		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);

		/* Allow settle */

		usleep_range(1, 5);

		/* CS override drive disable */

		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);

	}



	dw_spi_set_cs(spi, enable);

}



static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,

				   struct dw_spi_mmio *dwsmmio)

{

	const char *syscon_name = "microchip,sparx5-cpu-syscon";

	struct device *dev = &pdev->dev;

	struct dw_spi_mscc *dwsmscc;



	if (!IS_ENABLED(CONFIG_SPI_MUX)) {

		dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");

		return -EOPNOTSUPP;

	}



	dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);

	if (!dwsmscc)

		return -ENOMEM;



	dwsmscc->syscon =

		syscon_regmap_lookup_by_compatible(syscon_name);

	if (IS_ERR(dwsmscc->syscon)) {

		dev_err(dev, "No syscon map %s\n", syscon_name);

		return PTR_ERR(dwsmscc->syscon);

	}



	dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;

	dwsmmio->priv = dwsmscc;



	/* Register hook to configure CTRLR0 */

	dwsmmio->dws.update_cr0 = dw_spi_update_cr0;



	return 0;

}



static int dw_spi_alpine_init(struct platform_device *pdev,

			      struct dw_spi_mmio *dwsmmio)

{
@@ -297,6 +364,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { 
	{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},

	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},

	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},

	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},

	{ /* end of table */}

};

MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);