Commit 537fef80 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: Fix range size vs end confusion 



The fourth param is size, rather than range_end.

Note that we could increase the address space size if we had a way to
prevent buffers from spanning a 4G split, mostly just to avoid fw bugs
with 64b math.

Fixes: 84c31ee1 ("drm/msm/a6xx: Add support for per-instance pagetables")
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20220407202836.1211268-1-robdclark@gmail.com


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 0fe35b8d

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu) 
		return ERR_CAST(mmu);



	return msm_gem_address_space_create(mmu,

		"gpu", 0x100000000ULL, 0x1ffffffffULL);

		"gpu", 0x100000000ULL, SZ_4G);

}



static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)