Commit 53658de4 authored by Nick Hawkins's avatar Nick Hawkins Committed by Arnd Bergmann
Browse files

ARM: dts: Introduce HPE GXP Device tree



The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.

The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.

Signed-off-by: default avatarNick Hawkins <nick.hawkins@hpe.com>

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent b1d81dca
Loading
Loading
Loading
Loading
+2 −0
Original line number Diff line number Diff line
@@ -255,6 +255,8 @@ dtb-$(CONFIG_ARCH_HISI) += \
	hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
	hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HPE_GXP) += \
	hpe-bmc-dl360gen10.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
	integratorap.dtb \
	integratorap-im-pd1.dtb \
+26 −0
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for HPE DL360Gen10
 */

/include/ "hpe-gxp.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
	model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";

	aliases {
		serial0 = &uartc;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x20000000>;
	};
};
+127 −0
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for HPE GXP
 */

/dts-v1/;
/ {
	model = "Hewlett Packard Enterprise GXP BMC";
	compatible = "hpe,gxp";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L2>;
		};
	};

	clocks {
		pll: clock-0 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1600000000>;
		};

		iopclk: clock-1 {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clocks = <&pll>;
		};
	};

	axi {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		dma-ranges;

		L2: cache-controller@b0040000 {
			compatible = "arm,pl310-cache";
			reg = <0xb0040000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		ahb@c0000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc0000000 0x30000000>;
			dma-ranges;

			vic0: interrupt-controller@eff0000 {
				compatible = "arm,pl192-vic";
				reg = <0xeff0000 0x1000>;
				interrupt-controller;
				#interrupt-cells = <1>;
			};

			vic1: interrupt-controller@80f00000 {
				compatible = "arm,pl192-vic";
				reg = <0x80f00000 0x1000>;
				interrupt-controller;
				#interrupt-cells = <1>;
			};

			uarta: serial@e0 {
				compatible = "ns16550a";
				reg = <0xe0 0x8>;
				interrupts = <17>;
				interrupt-parent = <&vic0>;
				clock-frequency = <1846153>;
				reg-shift = <0>;
			};

			uartb: serial@e8 {
				compatible = "ns16550a";
				reg = <0xe8 0x8>;
				interrupts = <18>;
				interrupt-parent = <&vic0>;
				clock-frequency = <1846153>;
				reg-shift = <0>;
			};

			uartc: serial@f0 {
				compatible = "ns16550a";
				reg = <0xf0 0x8>;
				interrupts = <19>;
				interrupt-parent = <&vic0>;
				clock-frequency = <1846153>;
				reg-shift = <0>;
			};

			usb0: usb@efe0000 {
				compatible = "hpe,gxp-ehci", "generic-ehci";
				reg = <0xefe0000 0x100>;
				interrupts = <7>;
				interrupt-parent = <&vic0>;
			};

			st: timer@80 {
				compatible = "hpe,gxp-timer";
				reg = <0x80 0x16>;
				interrupts = <0>;
				interrupt-parent = <&vic0>;
				clocks = <&iopclk>;
				clock-names = "iop";
			};

			usb1: usb@efe0100 {
				compatible = "hpe,gxp-ohci", "generic-ohci";
				reg = <0xefe0100 0x110>;
				interrupts = <6>;
				interrupt-parent = <&vic0>;
			};
		};
	};
};