Commit 5334087e authored by Loic Poulain's avatar Loic Poulain Committed by Dmitry Baryshkov
Browse files

drm/msm: add support for QCM2290 MDSS 



Add compatibility for QCM2290 display subsystem, including
required entries in DPU hw catalog.

Signed-off-by: default avatarLoic Poulain <loic.poulain@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/474087/
Link: https://lore.kernel.org/r/1644852547-10067-1-git-send-email-loic.poulain@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 050770cb

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+148 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#define VIG_SM8250_MASK \

	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))



#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))



#define DMA_MSM8998_MASK \

	(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\

	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -336,6 +338,17 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = { 
	},

};



static const struct dpu_caps qcm2290_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0x4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,

	.ubwc_version = DPU_HW_UBWC_VER_20,

	.has_dim_layer = true,

	.has_idle_pc = true,

	.max_linewidth = 2160,

	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,

};



static const struct dpu_mdp_cfg sdm845_mdp[] = {

	{

	.name = "top_0", .id = MDP_TOP,
@@ -446,6 +459,19 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { 
	},

};



static const struct dpu_mdp_cfg qcm2290_mdp[] = {

	{

	.name = "top_0", .id = MDP_TOP,

	.base = 0x0, .len = 0x494,

	.features = 0,

	.highest_bank_bit = 0x2,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

		.reg_off = 0x2AC, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {

		.reg_off = 0x2AC, .bit_off = 8},

	},

};



/*************************************************************

 * CTL sub blocks config

 *************************************************************/
@@ -602,6 +628,15 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { 
	},

};



static const struct dpu_ctl_cfg qcm2290_ctl[] = {

	{

	.name = "ctl_0", .id = CTL_0,

	.base = 0x1000, .len = 0x1dc,

	.features = BIT(DPU_CTL_ACTIVE_CFG),

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	},

};



/*************************************************************

 * SSPP sub blocks config

 *************************************************************/
@@ -766,6 +801,30 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { 
		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),

};





#define _VIG_SBLK_NOSCALE(num, sdma_pri) \

	{ \

	.maxdwnscale = SSPP_UNITY_SCALE, \

	.maxupscale = SSPP_UNITY_SCALE, \

	.smart_dma_priority = sdma_pri, \

	.src_blk = {.name = STRCAT("sspp_src_", num), \

		.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \

	.format_list = plane_formats_yuv, \

	.num_formats = ARRAY_SIZE(plane_formats_yuv), \

	.virt_format_list = plane_formats, \

	.virt_num_formats = ARRAY_SIZE(plane_formats), \

	}



static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);

static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);



static const struct dpu_sspp_cfg qcm2290_sspp[] = {

	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,

		 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),

	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,

		 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),

};



/*************************************************************

 * MIXER sub blocks config

 *************************************************************/
@@ -876,6 +935,21 @@ static const struct dpu_lm_cfg sc7280_lm[] = { 
		&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),

};



/* QCM2290 */



static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {

	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.maxblendstages = 4, /* excluding base layer */

	.blendstage_base = { /* offsets relative to mixer base */

		0x20, 0x38, 0x50, 0x68

	},

};



static const struct dpu_lm_cfg qcm2290_lm[] = {

	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,

		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),

};



/*************************************************************

 * DSPP sub blocks config

 *************************************************************/
@@ -927,6 +1001,11 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = { 
		 &sm8150_dspp_sblk),

};



static const struct dpu_dspp_cfg qcm2290_dspp[] = {

	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,

		 &sm8150_dspp_sblk),

};



/*************************************************************

 * PINGPONG sub blocks config

 *************************************************************/
@@ -1009,6 +1088,12 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { 
			-1),

};



static struct dpu_pingpong_cfg qcm2290_pp[] = {

	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,

		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),

};



/*************************************************************

 * MERGE_3D sub blocks config

 *************************************************************/
@@ -1089,6 +1174,11 @@ static const struct dpu_intf_cfg sc8180x_intf[] = { 
	INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),

};



static const struct dpu_intf_cfg qcm2290_intf[] = {

	INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),

	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),

};



/*************************************************************

 * VBIF sub blocks config

 *************************************************************/
@@ -1234,6 +1324,10 @@ static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 
	{.fl = 4, .lut = 0x0000000000000357 },

};



static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {

	{.fl = 0, .lut = 0x0011222222335777},

};



static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {

	{.fl = 10, .lut = 0x344556677},

	{.fl = 11, .lut = 0x3344556677},
@@ -1476,6 +1570,27 @@ static const struct dpu_perf_cfg sc7280_perf_data = { 
	.bw_inefficiency_factor = 120,

};



static const struct dpu_perf_cfg qcm2290_perf_data = {

	.max_bw_low = 2700000,

	.max_bw_high = 2700000,

	.min_core_ib = 1300000,

	.min_llcc_ib = 0,

	.min_dram_ib = 1600000,

	.min_prefill_lines = 24,

	.danger_lut_tbl = {0xff, 0x0, 0x0},

	.safe_lut_tbl = {0xfff0, 0x0, 0x0},

	.qos_lut_tbl = {

		{.nentry = ARRAY_SIZE(qcm2290_qos_linear),

		.entries = qcm2290_qos_linear

		},

	},

	.cdp_cfg = {

		{.rd_enable = 1, .wr_enable = 1},

		{.rd_enable = 1, .wr_enable = 0}

	},

	.clk_inefficiency_factor = 105,

	.bw_inefficiency_factor = 120,

};

/*************************************************************

 * Hardware catalog init

 *************************************************************/
@@ -1688,6 +1803,38 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 
	};

}





/*

 * qcm2290_cfg_init(): populate qcm2290 dpu sub-blocks reg offsets

 * and instance counts.

 */

static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg)

{

	*dpu_cfg = (struct dpu_mdss_cfg){

		.caps = &qcm2290_dpu_caps,

		.mdp_count = ARRAY_SIZE(qcm2290_mdp),

		.mdp = qcm2290_mdp,

		.ctl_count = ARRAY_SIZE(qcm2290_ctl),

		.ctl = qcm2290_ctl,

		.sspp_count = ARRAY_SIZE(qcm2290_sspp),

		.sspp = qcm2290_sspp,

		.mixer_count = ARRAY_SIZE(qcm2290_lm),

		.mixer = qcm2290_lm,

		.dspp_count = ARRAY_SIZE(qcm2290_dspp),

		.dspp = qcm2290_dspp,

		.pingpong_count = ARRAY_SIZE(qcm2290_pp),

		.pingpong = qcm2290_pp,

		.intf_count = ARRAY_SIZE(qcm2290_intf),

		.intf = qcm2290_intf,

		.vbif_count = ARRAY_SIZE(sdm845_vbif),

		.vbif = sdm845_vbif,

		.reg_dma_count = 1,

		.dma_cfg = sdm845_regdma,

		.perf = qcm2290_perf_data,

		.mdss_irqs = IRQ_SC7180_MASK,

	};

}



static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {

	{ .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init},

	{ .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init},
@@ -1698,6 +1845,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 
	{ .hw_rev = DPU_HW_VER_510, .cfg_init = sc8180x_cfg_init},

	{ .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init},

	{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},

	{ .hw_rev = DPU_HW_VER_650, .cfg_init = qcm2290_cfg_init},

	{ .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init},

};

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
#define DPU_HW_VER_510	DPU_HW_VER(5, 1, 1) /* sc8180 */

#define DPU_HW_VER_600	DPU_HW_VER(6, 0, 0) /* sm8250 */

#define DPU_HW_VER_620	DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */

#define DPU_HW_VER_650	DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */

#define DPU_HW_VER_720	DPU_HW_VER(7, 2, 0) /* sc7280 */



#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

+1 −0
Original line number Diff line number Diff line
@@ -1329,6 +1329,7 @@ static const struct dev_pm_ops dpu_pm_ops = { 


const struct of_device_id dpu_dt_match[] = {

	{ .compatible = "qcom,msm8998-dpu", },

	{ .compatible = "qcom,qcm2290-dpu", },

	{ .compatible = "qcom,sdm845-dpu", },

	{ .compatible = "qcom,sc7180-dpu", },

	{ .compatible = "qcom,sc7280-dpu", },

drivers/gpu/drm/msm/msm_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -1436,6 +1436,7 @@ static const struct of_device_id dt_match[] = { 
	{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },

	{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },

	{ .compatible = "qcom,msm8998-mdss", .data = (void *)KMS_DPU },

	{ .compatible = "qcom,qcm2290-mdss", .data = (void *)KMS_DPU },

	{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },

	{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },

	{ .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },