Commit 531d2644 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Various LED binding conversions and clean-ups. Convert the
     ir-spi-led, pwm-ir-tx, and gpio-ir-tx LED bindings to schemas.
     Consistently reference LED common.yaml or multi-led schemas and
     disallow undefined properties.

   - Convert IDT 89HPESx, pwm-clock, st,stmipid02, Xilinx PCIe hosts,
     and fsl,imx-fb bindings to schema

   - Add ata-generic, Broadcom u-boot environment, and dynamic MTD
     sub-partitions bindings.

   - Make all SPI based displays reference spi-peripheral-props.yaml

   - Fix some schema property regex's which should be fixed strings or
     were missing start/end anchors

   - Remove 'status' in examples, again...

  DT Core:

   - Fix a possible NULL dereference in overlay functions

   - Fix kexec reading 32-bit "linux,initrd-{start,end}" values (which
     never worked)

   - Add of_address_count() helper to count number of 'reg' entries

   - Support .dtso extension for DT overlay source files. Rename staging
     and unittest overlay files.

   - Update dtc to upstream v1.6.1-63-g55778a03df61"

* tag 'devicetree-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (42 commits)
  dt-bindings: leds: Add missing references to common LED schema
  dt-bindings: leds: intel,lgm: Add missing 'led-gpios' property
  of: overlay: fix null pointer dereferencing in find_dup_cset_node_entry() and find_dup_cset_prop()
  dt-bindings: lcdif: Fix constraints for imx8mp
  media: dt-bindings: atmel,isc: Drop unneeded unevaluatedProperties
  dt-bindings: Drop Jee Heng Sia
  dt-bindings: thermal: cooling-devices: Add missing cache related properties
  dt-bindings: leds: irled: ir-spi-led: convert to DT schema
  dt-bindings: leds: irled: pwm-ir-tx: convert to DT schema
  dt-bindings: leds: irled: gpio-ir-tx: convert to DT schema
  dt-bindings: leds: mt6360: rework to match multi-led
  dt-bindings: leds: lp55xx: rework to match multi-led
  dt-bindings: leds: lp55xx: switch to preferred 'gpios' suffix
  dt-bindings: leds: lp55xx: allow label
  dt-bindings: leds: use unevaluatedProperties for common.yaml
  dt-bindings: thermal: tsens: Add SM6115 compatible
  of/kexec: Fix reading 32-bit "linux,initrd-{start,end}" values
  dt-bindings: display: Convert fsl,imx-fb.txt to dt-schema
  dt-bindings: Add missing start and/or end of line regex anchors
  dt-bindings: qcom,pdc: Add missing compatibles
  ...
parents 4d03390b 580f9896

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

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@@ -47,5 +47,4 @@ examples: 
      compatible = "nvidia,tegra234-ccplex-cluster";

      reg = <0x0e000000 0x5ffff>;

      nvidia,bpmp = <&bpmp>;

      status = "okay";

    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml

+27 −27
Original line number Diff line number Diff line
@@ -123,6 +123,33 @@ properties: 
      some PLLs, clocks and then brings up CPU0 for resuming the

      system.



  core-supply:

    description:

      Phandle to voltage regulator connected to the SoC Core power rail.



  core-domain:

    type: object

    description: |

      The vast majority of hardware blocks of Tegra SoC belong to a

      Core power domain, which has a dedicated voltage rail that powers

      the blocks.



    properties:

      operating-points-v2:

        description:

          Should contain level, voltages and opp-supported-hw property.

          The supported-hw is a bitfield indicating SoC speedo or process

          ID mask.



      "#power-domain-cells":

        const: 0



    required:

      - operating-points-v2

      - "#power-domain-cells"



    additionalProperties: false



  i2c-thermtrip:

    type: object

    description:
@@ -300,33 +327,6 @@ patternProperties: 


    additionalProperties: false



  core-domain:

    type: object

    description: |

      The vast majority of hardware blocks of Tegra SoC belong to a

      Core power domain, which has a dedicated voltage rail that powers

      the blocks.



    properties:

      operating-points-v2:

        description:

          Should contain level, voltages and opp-supported-hw property.

          The supported-hw is a bitfield indicating SoC speedo or process

          ID mask.



      "#power-domain-cells":

        const: 0



    required:

      - operating-points-v2

      - "#power-domain-cells"



    additionalProperties: false



  core-supply:

    description:

      Phandle to voltage regulator connected to the SoC Core power rail.



required:

  - compatible

  - reg

Documentation/devicetree/bindings/ata/ata-generic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/ata-generic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Generic Parallel ATA Controller



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description:

  Generic Parallel ATA controllers supporting PIO modes only.



properties:

  compatible:

    items:

      - enum:

          - arm,vexpress-cf

          - fsl,mpc8349emitx-pata

      - const: ata-generic



  reg:

    items:

      - description: Command interface registers

      - description: Control interface registers



  reg-shift:

    enum: [ 1, 2 ]



  interrupts:

    maxItems: 1



  ata-generic,use16bit:

    type: boolean

    description: Use 16-bit accesses instead of 32-bit for data transfers



  pio-mode:

    description: Maximum ATA PIO transfer mode

    $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 6

    default: 0



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    compact-flash@1a000 {

        compatible = "arm,vexpress-cf", "ata-generic";

        reg = <0x1a000 0x100>,

              <0x1a100 0xf00>;

        reg-shift = <2>;

    };

...

Documentation/devicetree/bindings/clock/pwm-clock.txt

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Binding for an external clock signal driven by a PWM pin.



This binding uses the common clock binding[1] and the common PWM binding[2].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] Documentation/devicetree/bindings/pwm/pwm.txt



Required properties:

- compatible : shall be "pwm-clock".

- #clock-cells : from common clock binding; shall be set to 0.

- pwms : from common PWM binding; this determines the clock frequency

  via the period given in the PWM specifier.



Optional properties:

- clock-output-names : From common clock binding.

- clock-frequency : Exact output frequency, in case the PWM period

  is not exact but was rounded to nanoseconds.



Example:

	clock {

		compatible = "pwm-clock";

		#clock-cells = <0>;

		clock-frequency = <25000000>;

		clock-output-names = "mipi_mclk";

		pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */

	};

Documentation/devicetree/bindings/clock/pwm-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/pwm-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: An external clock signal driven by a PWM pin.



maintainers:

  - Philipp Zabel <p.zabel@pengutronix.de>



properties:

  compatible:

    const: pwm-clock



  '#clock-cells':

    const: 0



  clock-frequency:

    description: Exact output frequency, in case the PWM period is not exact

      but was rounded to nanoseconds.



  clock-output-names:

    maxItems: 1



  pwms:

    maxItems: 1



required:

  - compatible

  - '#clock-cells'

  - pwms



additionalProperties: false



examples:

  - |

    clock {

        compatible = "pwm-clock";

        #clock-cells = <0>;

        clock-frequency = <25000000>;

        clock-output-names = "mipi_mclk";

        pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */

    };

...