Commit 530d5ce2 authored by Maxim Mikityanskiy's avatar Maxim Mikityanskiy Committed by Saeed Mahameed
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net/mlx5e: Generalize TX MPWQE checks for full session 



As preparation for the upcoming TX MPWQE for SKBs, create a function
(mlx5e_tx_mpwqe_is_full) to check whether an MPWQE session is full. This
function will be shared by MPWQE code for XDP and for SKBs. Defines are
renamed and moved to make them not XDP-specific.

Signed-off-by: default avatarMaxim Mikityanskiy <maximmi@mellanox.com>
Reviewed-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 338c46c6

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h

+18 −0
Original line number Diff line number Diff line
@@ -9,6 +9,19 @@ 


#define MLX5E_TX_WQE_EMPTY_DS_COUNT (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS)



/* The mult of MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS

 * (16 * 4 == 64) does not fit in the 6-bit DS field of Ctrl Segment.

 * We use a bound lower that MLX5_SEND_WQE_MAX_WQEBBS to let a

 * full-session WQE be cache-aligned.

 */

#if L1_CACHE_BYTES < 128

#define MLX5E_TX_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 1)

#else

#define MLX5E_TX_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 2)

#endif



#define MLX5E_TX_MPW_MAX_NUM_DS (MLX5E_TX_MPW_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS)



#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))



enum mlx5e_icosq_wqe_type {
@@ -266,6 +279,11 @@ mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq_dma *dma) 


void mlx5e_sq_xmit_simple(struct mlx5e_txqsq *sq, struct sk_buff *skb, bool xmit_more);



static inline bool mlx5e_tx_mpwqe_is_full(struct mlx5e_xdp_mpwqe *session)

{

	return session->ds_count == MLX5E_TX_MPW_MAX_NUM_DS;

}



static inline void mlx5e_rqwq_reset(struct mlx5e_rq *rq)

{

	if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c

+1 −1
Original line number Diff line number Diff line
@@ -199,7 +199,7 @@ static void mlx5e_xdp_mpwqe_session_start(struct mlx5e_xdpsq *sq) 
	struct mlx5e_tx_wqe *wqe;

	u16 pi;



	pi = mlx5e_xdpsq_get_next_pi(sq, MLX5E_XDP_MPW_MAX_WQEBBS);

	pi = mlx5e_xdpsq_get_next_pi(sq, MLX5E_TX_MPW_MAX_WQEBBS);

	wqe = MLX5E_TX_FETCH_WQE(sq, pi);

	net_prefetchw(wqe->data);

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h

+2 −16
Original line number Diff line number Diff line
@@ -45,20 +45,6 @@ 
	(MLX5E_XDP_INLINE_WQE_MAX_DS_CNT * MLX5_SEND_WQE_DS - \

	 sizeof(struct mlx5_wqe_inline_seg))



/* The mult of MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS

 * (16 * 4 == 64) does not fit in the 6-bit DS field of Ctrl Segment.

 * We use a bound lower that MLX5_SEND_WQE_MAX_WQEBBS to let a

 * full-session WQE be cache-aligned.

 */

#if L1_CACHE_BYTES < 128

#define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 1)

#else

#define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 2)

#endif



#define MLX5E_XDP_MPW_MAX_NUM_DS \

	(MLX5E_XDP_MPW_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS)



struct mlx5e_xsk_param;

int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk);

bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct mlx5e_dma_info *di,
@@ -141,8 +127,8 @@ static inline bool mlx5e_xdp_mpqwe_is_full(struct mlx5e_xdp_mpwqe *session) 
{

	if (session->inline_on)

		return session->ds_count + MLX5E_XDP_INLINE_WQE_MAX_DS_CNT >

		       MLX5E_XDP_MPW_MAX_NUM_DS;

	return session->ds_count == MLX5E_XDP_MPW_MAX_NUM_DS;

		       MLX5E_TX_MPW_MAX_NUM_DS;

	return mlx5e_tx_mpwqe_is_full(session);

}



struct mlx5e_xdp_wqe_info {