Commit 53082d6c authored by Weili Qian's avatar Weili Qian Committed by JangShui Yang
Browse files

hisi_acc_vfio_pci: obtain the mailbox configuration at one time 

virt inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I9DRAC


CVE: NA

----------------------------------------------------------------------

The mailbox configuration(128 bits) needs to be obtained from
the hardware at one time. If the mailbox configuration is
obtained for multiple times, the read value may be incorrect.
Use the instruction to read mailbox data instead of readl().

Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent 68790cc5

drivers/crypto/hisilicon/qm.c

+8 −7
Original line number Diff line number Diff line
@@ -662,7 +662,7 @@ static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) 
	return ret;

}



int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,

int hisi_qm_mb_write(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,

	       bool op)

{

	struct qm_mailbox mailbox;
@@ -682,9 +682,9 @@ int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, 


	return ret;

}

EXPORT_SYMBOL_GPL(hisi_qm_mb);

EXPORT_SYMBOL_GPL(hisi_qm_mb_write);



static int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue)

int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue)

{

	struct qm_mailbox mailbox;

	int ret;
@@ -701,6 +701,7 @@ static int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue) 


	return 0;

}

EXPORT_SYMBOL_GPL(hisi_qm_mb_read);



/* op 0: set xqc information to hardware, 1: get xqc information from hardware. */

int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op)
@@ -1789,12 +1790,12 @@ static int qm_ping_pf(struct hisi_qm *qm, u64 cmd) 


static int qm_drain_qm(struct hisi_qm *qm)

{

	return hisi_qm_mb(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0);

	return hisi_qm_mb_write(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0);

}



static int qm_stop_qp(struct hisi_qp *qp)

{

	return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);

	return hisi_qm_mb_write(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);

}



static int qm_set_msi(struct hisi_qm *qm, bool set)
@@ -3164,11 +3165,11 @@ static int __hisi_qm_start(struct hisi_qm *qm) 
	if (ret)

		return ret;



	ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

	ret = hisi_qm_mb_write(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

	if (ret)

		return ret;



	ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

	ret = hisi_qm_mb_write(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

	if (ret)

		return ret;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

+6 −39
Original line number Diff line number Diff line
@@ -81,13 +81,10 @@ static int qm_get_vft(struct hisi_qm *qm, u32 *base) 
	u32 qp_num;

	int ret;



	ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);

	ret = hisi_qm_mb_read(qm, &sqc_vft, QM_MB_CMD_SQC_VFT_V2, 0);

	if (ret)

		return ret;



	sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

		  QM_XQC_ADDR_OFFSET);

	*base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);

	qp_num = (QM_SQC_VFT_NUM_MASK_V2 &

		  (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
@@ -95,36 +92,6 @@ static int qm_get_vft(struct hisi_qm *qm, u32 *base) 
	return qp_num;

}



static int qm_get_sqc(struct hisi_qm *qm, u64 *addr)

{

	int ret;



	ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, 0, 0, 1);

	if (ret)

		return ret;



	*addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

		  QM_XQC_ADDR_OFFSET);



	return 0;

}



static int qm_get_cqc(struct hisi_qm *qm, u64 *addr)

{

	int ret;



	ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, 0, 0, 1);

	if (ret)

		return ret;



	*addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

		  QM_XQC_ADDR_OFFSET);



	return 0;

}



static int qm_get_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data)

{

	struct device *dev = &qm->pdev->dev;
@@ -347,7 +314,7 @@ static void vf_qm_fun_reset(struct hisi_qm *qm) 


static int vf_qm_func_stop(struct hisi_qm *qm)

{

	return hisi_qm_mb(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0);

	return hisi_qm_mb_write(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0);

}



static int vf_qm_check_match(struct hisi_acc_vf_core_device *hisi_acc_vdev,
@@ -486,13 +453,13 @@ static int vf_qm_load_data(struct hisi_acc_vf_core_device *hisi_acc_vdev, 
		return ret;

	}



	ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

	ret = hisi_qm_mb_write(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

	if (ret) {

		dev_err(dev, "set sqc failed\n");

		return ret;

	}



	ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

	ret = hisi_qm_mb_write(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

	if (ret) {

		dev_err(dev, "set cqc failed\n");

		return ret;
@@ -534,13 +501,13 @@ static int vf_qm_state_save(struct hisi_acc_vf_core_device *hisi_acc_vdev, 
	vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[QM_XQC_ADDR_LOW];



	/* Through SQC_BT/CQC_BT to get sqc and cqc address */

	ret = qm_get_sqc(vf_qm, &vf_data->sqc_dma);

	ret = hisi_qm_mb_read(vf_qm, &vf_data->sqc_dma, QM_MB_CMD_SQC_BT, 0);

	if (ret) {

		dev_err(dev, "failed to read SQC addr!\n");

		return -EINVAL;

	}



	ret = qm_get_cqc(vf_qm, &vf_data->cqc_dma);

	ret = hisi_qm_mb_read(vf_qm, &vf_data->cqc_dma, QM_MB_CMD_CQC_BT, 0);

	if (ret) {

		dev_err(dev, "failed to read CQC addr!\n");

		return -EINVAL;

include/linux/hisi_acc_qm.h

+3 −5
Original line number Diff line number Diff line
@@ -52,8 +52,6 @@ 
#define QM_MB_EVENT_SHIFT               8

#define QM_MB_BUSY_SHIFT		13

#define QM_MB_OP_SHIFT			14

#define QM_MB_CMD_DATA_ADDR_L		0x304

#define QM_MB_CMD_DATA_ADDR_H		0x308



/* doorbell */

#define QM_DOORBELL_CMD_SQ              0
@@ -559,9 +557,9 @@ void hisi_qm_reset_prepare(struct pci_dev *pdev); 
void hisi_qm_reset_done(struct pci_dev *pdev);



int hisi_qm_wait_mb_ready(struct hisi_qm *qm);

int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,

	       bool op);



int hisi_qm_mb_write(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr,

			       u16 queue, bool op);

int hisi_qm_mb_read(struct hisi_qm *qm, u64 *msg, u8 cmd, u16 queue);

struct hisi_acc_sgl_pool;

struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,

	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,