Commit 5305cc2c authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

KVM: arm64: nv: Add EL2 system registers to vcpu context 



Add the minimal set of EL2 system registers to the vcpu context.
Nothing uses them just yet.

Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Reviewed-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230209175820.1939006-7-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 1d05d51b

arch/arm64/include/asm/kvm_host.h

+32 −1
Original line number Diff line number Diff line
@@ -325,12 +325,43 @@ enum vcpu_sysreg { 
	TFSR_EL1,	/* Tag Fault Status Register (EL1) */

	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */



	/* 32bit specific registers. Keep them at the end of the range */

	/* 32bit specific registers. */

	DACR32_EL2,	/* Domain Access Control Register */

	IFSR32_EL2,	/* Instruction Fault Status Register */

	FPEXC32_EL2,	/* Floating-Point Exception Control Register */

	DBGVCR32_EL2,	/* Debug Vector Catch Register */



	/* EL2 registers */

	VPIDR_EL2,	/* Virtualization Processor ID Register */

	VMPIDR_EL2,	/* Virtualization Multiprocessor ID Register */

	SCTLR_EL2,	/* System Control Register (EL2) */

	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */

	HCR_EL2,	/* Hypervisor Configuration Register */

	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */

	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */

	HSTR_EL2,	/* Hypervisor System Trap Register */

	HACR_EL2,	/* Hypervisor Auxiliary Control Register */

	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */

	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */

	TCR_EL2,	/* Translation Control Register (EL2) */

	VTTBR_EL2,	/* Virtualization Translation Table Base Register */

	VTCR_EL2,	/* Virtualization Translation Control Register */

	SPSR_EL2,	/* EL2 saved program status register */

	ELR_EL2,	/* EL2 exception link register */

	AFSR0_EL2,	/* Auxiliary Fault Status Register 0 (EL2) */

	AFSR1_EL2,	/* Auxiliary Fault Status Register 1 (EL2) */

	ESR_EL2,	/* Exception Syndrome Register (EL2) */

	FAR_EL2,	/* Fault Address Register (EL2) */

	HPFAR_EL2,	/* Hypervisor IPA Fault Address Register */

	MAIR_EL2,	/* Memory Attribute Indirection Register (EL2) */

	AMAIR_EL2,	/* Auxiliary Memory Attribute Indirection Register (EL2) */

	VBAR_EL2,	/* Vector Base Address Register (EL2) */

	RVBAR_EL2,	/* Reset Vector Base Address Register */

	CONTEXTIDR_EL2,	/* Context ID Register (EL2) */

	TPIDR_EL2,	/* EL2 Software Thread ID Register */

	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */

	SP_EL2,		/* EL2 Stack Pointer */



	NR_SYS_REGS	/* Nothing after this line! */

};