Commit 52d45575 authored by Ido Schimmel's avatar Ido Schimmel Committed by Jakub Kicinski
Browse files

mlxsw: spectrum_router: Use different trap identifier for unresolved nexthops 



Unresolved nexthops are currently written to the adjacency table with a
discard action. Packets hitting such entries are trapped to the CPU via
the 'DISCARD_ROUTER3' trap which can be enabled or disabled on demand,
but is always enabled in order to ensure the kernel can resolve the
unresolved neighbours.

This trap will be needed for blackhole nexthops support. Therefore, move
unresolved nexthops to explicitly program the adjacency entries with a
trap action and a different trap identifier, 'RTR_EGRESS0'.

Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 07c78536

drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c

+2 −1
Original line number Diff line number Diff line
@@ -5008,11 +5008,12 @@ static int mlxsw_sp_adj_discard_write(struct mlxsw_sp *mlxsw_sp, u16 rif_index) 
	if (err)

		return err;



	trap_action = MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS;

	trap_action = MLXSW_REG_RATR_TRAP_ACTION_TRAP;

	mlxsw_reg_ratr_pack(ratr_pl, MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY, true,

			    MLXSW_REG_RATR_TYPE_ETHERNET,

			    mlxsw_sp->router->adj_discard_index, rif_index);

	mlxsw_reg_ratr_trap_action_set(ratr_pl, trap_action);

	mlxsw_reg_ratr_trap_id_set(ratr_pl, MLXSW_TRAP_ID_RTR_EGRESS0);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ratr), ratr_pl);

	if (err)

		goto err_ratr_write;

drivers/net/ethernet/mellanox/mlxsw/spectrum_trap.c

+1 −1
Original line number Diff line number Diff line
@@ -617,7 +617,7 @@ static const struct mlxsw_sp_trap_item mlxsw_sp_trap_items_arr[] = { 
					       TRAP_TO_CPU),

			MLXSW_SP_RXL_EXCEPTION(HOST_MISS_IPV6, L3_EXCEPTIONS,

					       TRAP_TO_CPU),

			MLXSW_SP_RXL_EXCEPTION(DISCARD_ROUTER3, L3_EXCEPTIONS,

			MLXSW_SP_RXL_EXCEPTION(RTR_EGRESS0, L3_EXCEPTIONS,

					       TRAP_EXCEPTION_TO_CPU),

		},

	},

drivers/net/ethernet/mellanox/mlxsw/trap.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ enum { 
	MLXSW_TRAP_ID_RTR_INGRESS1 = 0x71,

	MLXSW_TRAP_ID_IPV6_PIM = 0x79,

	MLXSW_TRAP_ID_IPV6_VRRP = 0x7A,

	MLXSW_TRAP_ID_RTR_EGRESS0 = 0x80,

	MLXSW_TRAP_ID_IPV4_BGP = 0x88,

	MLXSW_TRAP_ID_IPV6_BGP = 0x89,

	MLXSW_TRAP_ID_L3_IPV6_ROUTER_SOLICITATION = 0x8A,