Commit 5272b7fc authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/switchtec' 

  - Support 64-bit addressing for both streaming and coherent DMA (Wesley
    Sheng)

  - Read vep_vector_number with 16-bit, not 32-bit read (Logan Gunthorpe)

  - Add Intercomm Notify and Upstream Error Containment support (Logan
    Gunthorpe)

  - Remove redundant valid PFF number count (Wesley Sheng)

  - Avoid unnecessary CSR read in ISR (Wesley Sheng)

  - Rename Gen3-specific constants (Logan Gunthorpe)

  - Rework infrastructure to support Gen3- and Gen4-specific code (Logan
    Gunthorpe)

  - Add Gen4 system info register support (Logan Gunthorpe)

  - Add Gen4 flash information interface support (Kelvin Cao)

  - Add Gen4 MRPC GAS access permission check (Kelvin Cao)

* pci/switchtec:
  PCI/switchtec: Add Gen4 device IDs
  PCI/switchtec: Add Gen4 MRPC GAS access permission check
  PCI/switchtec: Add Gen4 flash information interface support
  PCI/switchtec: Add Gen4 system info register support
  PCI/switchtec: Separate Gen3 register structures into unions
  PCI/switchtec: Factor out Gen3 ioctl_flash_part_info()
  PCI/switchtec: Add 'generation' variable
  PCI/switchtec: Rename generation-specific constants
  PCI/switchtec: Move check event ID from mask_event() to switchtec_event_isr()
  PCI/switchtec: Remove redundant valid PFF number count
  PCI/switchtec: Add support for Intercomm Notify and Upstream Error Containment
  PCI/switchtec: Fix vep_vector_number ioread width
  PCI/switchtec: Use dma_set_mask_and_coherent()
parents cee538f6 7a30ebb9

drivers/pci/quirks.c

+18 −0
Original line number Diff line number Diff line
@@ -5368,6 +5368,24 @@ SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 
SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */

SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */

SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */

SWITCHTEC_QUIRK(0x4000);  /* PFX 100XG4 */

SWITCHTEC_QUIRK(0x4084);  /* PFX 84XG4  */

SWITCHTEC_QUIRK(0x4068);  /* PFX 68XG4  */

SWITCHTEC_QUIRK(0x4052);  /* PFX 52XG4  */

SWITCHTEC_QUIRK(0x4036);  /* PFX 36XG4  */

SWITCHTEC_QUIRK(0x4028);  /* PFX 28XG4  */

SWITCHTEC_QUIRK(0x4100);  /* PSX 100XG4 */

SWITCHTEC_QUIRK(0x4184);  /* PSX 84XG4  */

SWITCHTEC_QUIRK(0x4168);  /* PSX 68XG4  */

SWITCHTEC_QUIRK(0x4152);  /* PSX 52XG4  */

SWITCHTEC_QUIRK(0x4136);  /* PSX 36XG4  */

SWITCHTEC_QUIRK(0x4128);  /* PSX 28XG4  */

SWITCHTEC_QUIRK(0x4200);  /* PAX 100XG4 */

SWITCHTEC_QUIRK(0x4284);  /* PAX 84XG4  */

SWITCHTEC_QUIRK(0x4268);  /* PAX 68XG4  */

SWITCHTEC_QUIRK(0x4252);  /* PAX 52XG4  */

SWITCHTEC_QUIRK(0x4236);  /* PAX 36XG4  */

SWITCHTEC_QUIRK(0x4228);  /* PAX 28XG4  */



/*

 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does

drivers/pci/switch/switchtec.c

+284 −86
Original line number Diff line number Diff line
@@ -317,8 +317,15 @@ static ssize_t field ## _show(struct device *dev, \ 
	struct device_attribute *attr, char *buf) \

{ \

	struct switchtec_dev *stdev = to_stdev(dev); \

	return io_string_show(buf, &stdev->mmio_sys_info->field, \

			    sizeof(stdev->mmio_sys_info->field)); \

	struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \

	if (stdev->gen == SWITCHTEC_GEN3) \

		return io_string_show(buf, &si->gen3.field, \

				      sizeof(si->gen3.field)); \

	else if (stdev->gen == SWITCHTEC_GEN4) \

		return io_string_show(buf, &si->gen4.field, \

				      sizeof(si->gen4.field)); \

	else \

		return -ENOTSUPP; \

} \

\

static DEVICE_ATTR_RO(field)
@@ -326,13 +333,31 @@ static DEVICE_ATTR_RO(field) 
DEVICE_ATTR_SYS_INFO_STR(vendor_id);

DEVICE_ATTR_SYS_INFO_STR(product_id);

DEVICE_ATTR_SYS_INFO_STR(product_revision);

DEVICE_ATTR_SYS_INFO_STR(component_vendor);



static ssize_t component_vendor_show(struct device *dev,

				     struct device_attribute *attr, char *buf)

{

	struct switchtec_dev *stdev = to_stdev(dev);

	struct sys_info_regs __iomem *si = stdev->mmio_sys_info;



	/* component_vendor field not supported after gen3 */

	if (stdev->gen != SWITCHTEC_GEN3)

		return sprintf(buf, "none\n");



	return io_string_show(buf, &si->gen3.component_vendor,

			      sizeof(si->gen3.component_vendor));

}

static DEVICE_ATTR_RO(component_vendor);



static ssize_t component_id_show(struct device *dev,

	struct device_attribute *attr, char *buf)

{

	struct switchtec_dev *stdev = to_stdev(dev);

	int id = ioread16(&stdev->mmio_sys_info->component_id);

	int id = ioread16(&stdev->mmio_sys_info->gen3.component_id);



	/* component_id field not supported after gen3 */

	if (stdev->gen != SWITCHTEC_GEN3)

		return sprintf(buf, "none\n");



	return sprintf(buf, "PM%04X\n", id);

}
@@ -342,7 +367,11 @@ static ssize_t component_revision_show(struct device *dev, 
	struct device_attribute *attr, char *buf)

{

	struct switchtec_dev *stdev = to_stdev(dev);

	int rev = ioread8(&stdev->mmio_sys_info->component_revision);

	int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision);



	/* component_revision field not supported after gen3 */

	if (stdev->gen != SWITCHTEC_GEN3)

		return sprintf(buf, "255\n");



	return sprintf(buf, "%d\n", rev);

}
@@ -450,6 +479,12 @@ static ssize_t switchtec_dev_write(struct file *filp, const char __user *data, 
		rc = -EFAULT;

		goto out;

	}

	if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) ||

	     (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) &&

	    !capable(CAP_SYS_ADMIN)) {

		rc = -EPERM;

		goto out;

	}



	data += sizeof(stuser->cmd);

	rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd));
@@ -568,8 +603,15 @@ static int ioctl_flash_info(struct switchtec_dev *stdev, 
	struct switchtec_ioctl_flash_info info = {0};

	struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;



	info.flash_length = ioread32(&fi->flash_length);

	info.num_partitions = SWITCHTEC_IOCTL_NUM_PARTITIONS;

	if (stdev->gen == SWITCHTEC_GEN3) {

		info.flash_length = ioread32(&fi->gen3.flash_length);

		info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3;

	} else if (stdev->gen == SWITCHTEC_GEN4) {

		info.flash_length = ioread32(&fi->gen4.flash_length);

		info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4;

	} else {

		return -ENOTSUPP;

	}



	if (copy_to_user(uinfo, &info, sizeof(info)))

		return -EFAULT;
@@ -584,75 +626,200 @@ static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info, 
	info->length = ioread32(&pi->length);

}



static int ioctl_flash_part_info(struct switchtec_dev *stdev,

	struct switchtec_ioctl_flash_part_info __user *uinfo)

static int flash_part_info_gen3(struct switchtec_dev *stdev,

		struct switchtec_ioctl_flash_part_info *info)

{

	struct switchtec_ioctl_flash_part_info info = {0};

	struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;

	struct sys_info_regs __iomem *si = stdev->mmio_sys_info;

	struct flash_info_regs_gen3 __iomem *fi =

		&stdev->mmio_flash_info->gen3;

	struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3;

	u32 active_addr = -1;



	if (copy_from_user(&info, uinfo, sizeof(info)))

		return -EFAULT;



	switch (info.flash_partition) {

	switch (info->flash_partition) {

	case SWITCHTEC_IOCTL_PART_CFG0:

		active_addr = ioread32(&fi->active_cfg);

		set_fw_info_part(&info, &fi->cfg0);

		if (ioread16(&si->cfg_running) == SWITCHTEC_CFG0_RUNNING)

			info.active |= SWITCHTEC_IOCTL_PART_RUNNING;

		set_fw_info_part(info, &fi->cfg0);

		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_CFG1:

		active_addr = ioread32(&fi->active_cfg);

		set_fw_info_part(&info, &fi->cfg1);

		if (ioread16(&si->cfg_running) == SWITCHTEC_CFG1_RUNNING)

			info.active |= SWITCHTEC_IOCTL_PART_RUNNING;

		set_fw_info_part(info, &fi->cfg1);

		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_IMG0:

		active_addr = ioread32(&fi->active_img);

		set_fw_info_part(&info, &fi->img0);

		if (ioread16(&si->img_running) == SWITCHTEC_IMG0_RUNNING)

			info.active |= SWITCHTEC_IOCTL_PART_RUNNING;

		set_fw_info_part(info, &fi->img0);

		if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_IMG1:

		active_addr = ioread32(&fi->active_img);

		set_fw_info_part(&info, &fi->img1);

		if (ioread16(&si->img_running) == SWITCHTEC_IMG1_RUNNING)

			info.active |= SWITCHTEC_IOCTL_PART_RUNNING;

		set_fw_info_part(info, &fi->img1);

		if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_NVLOG:

		set_fw_info_part(info, &fi->nvlog);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR0:

		set_fw_info_part(info, &fi->vendor[0]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR1:

		set_fw_info_part(info, &fi->vendor[1]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR2:

		set_fw_info_part(info, &fi->vendor[2]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR3:

		set_fw_info_part(info, &fi->vendor[3]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR4:

		set_fw_info_part(info, &fi->vendor[4]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR5:

		set_fw_info_part(info, &fi->vendor[5]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR6:

		set_fw_info_part(info, &fi->vendor[6]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR7:

		set_fw_info_part(info, &fi->vendor[7]);

		break;

	default:

		return -EINVAL;

	}



	if (info->address == active_addr)

		info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;



	return 0;

}



static int flash_part_info_gen4(struct switchtec_dev *stdev,

		struct switchtec_ioctl_flash_part_info *info)

{

	struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4;

	struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4;

	struct active_partition_info_gen4 __iomem *af = &fi->active_flag;



	switch (info->flash_partition) {

	case SWITCHTEC_IOCTL_PART_MAP_0:

		set_fw_info_part(info, &fi->map0);

		break;

	case SWITCHTEC_IOCTL_PART_MAP_1:

		set_fw_info_part(info, &fi->map1);

		break;

	case SWITCHTEC_IOCTL_PART_KEY_0:

		set_fw_info_part(info, &fi->key0);

		if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_KEY_1:

		set_fw_info_part(info, &fi->key1);

		if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_BL2_0:

		set_fw_info_part(info, &fi->bl2_0);

		if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_BL2_1:

		set_fw_info_part(info, &fi->bl2_1);

		if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_CFG0:

		set_fw_info_part(info, &fi->cfg0);

		if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_CFG1:

		set_fw_info_part(info, &fi->cfg1);

		if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_IMG0:

		set_fw_info_part(info, &fi->img0);

		if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_IMG1:

		set_fw_info_part(info, &fi->img1);

		if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE)

			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;

		if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING)

			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;

		break;

	case SWITCHTEC_IOCTL_PART_NVLOG:

		set_fw_info_part(&info, &fi->nvlog);

		set_fw_info_part(info, &fi->nvlog);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR0:

		set_fw_info_part(&info, &fi->vendor[0]);

		set_fw_info_part(info, &fi->vendor[0]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR1:

		set_fw_info_part(&info, &fi->vendor[1]);

		set_fw_info_part(info, &fi->vendor[1]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR2:

		set_fw_info_part(&info, &fi->vendor[2]);

		set_fw_info_part(info, &fi->vendor[2]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR3:

		set_fw_info_part(&info, &fi->vendor[3]);

		set_fw_info_part(info, &fi->vendor[3]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR4:

		set_fw_info_part(&info, &fi->vendor[4]);

		set_fw_info_part(info, &fi->vendor[4]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR5:

		set_fw_info_part(&info, &fi->vendor[5]);

		set_fw_info_part(info, &fi->vendor[5]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR6:

		set_fw_info_part(&info, &fi->vendor[6]);

		set_fw_info_part(info, &fi->vendor[6]);

		break;

	case SWITCHTEC_IOCTL_PART_VENDOR7:

		set_fw_info_part(&info, &fi->vendor[7]);

		set_fw_info_part(info, &fi->vendor[7]);

		break;

	default:

		return -EINVAL;

	}



	if (info.address == active_addr)

		info.active |= SWITCHTEC_IOCTL_PART_ACTIVE;

	return 0;

}



static int ioctl_flash_part_info(struct switchtec_dev *stdev,

		struct switchtec_ioctl_flash_part_info __user *uinfo)

{

	int ret;

	struct switchtec_ioctl_flash_part_info info = {0};



	if (copy_from_user(&info, uinfo, sizeof(info)))

		return -EFAULT;



	if (stdev->gen == SWITCHTEC_GEN3) {

		ret = flash_part_info_gen3(stdev, &info);

		if (ret)

			return ret;

	} else if (stdev->gen == SWITCHTEC_GEN4) {

		ret = flash_part_info_gen4(stdev, &info);

		if (ret)

			return ret;

	} else {

		return -ENOTSUPP;

	}



	if (copy_to_user(uinfo, &info, sizeof(info)))

		return -EFAULT;
@@ -683,11 +850,7 @@ static int ioctl_event_summary(struct switchtec_dev *stdev, 
		s->part[i] = reg;

	}



	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {

		reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);

		if (reg != PCI_VENDOR_ID_MICROSEMI)

			break;



	for (i = 0; i < stdev->pff_csr_count; i++) {

		reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);

		s->pff[i] = reg;

	}
@@ -751,10 +914,13 @@ static const struct event_reg { 
	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),

	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),

	EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr),

	EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY,

	       intercomm_notify_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr),

	EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr),
@@ -1181,10 +1347,6 @@ static int mask_event(struct switchtec_dev *stdev, int eid, int idx) 
	if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))

		return 0;



	if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE ||

	    eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)

		return 0;



	dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);

	hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED);

	iowrite32(hdr, hdr_reg);
@@ -1231,8 +1393,13 @@ static irqreturn_t switchtec_event_isr(int irq, void *dev) 


	check_link_state_events(stdev);



	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++)

	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {

		if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE ||

		    eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)

			continue;



		event_count += mask_all_events(stdev, eid);

	}



	if (event_count) {

		atomic_inc(&stdev->event_cnt);
@@ -1276,7 +1443,7 @@ static int switchtec_init_isr(struct switchtec_dev *stdev) 
	if (nvecs < 0)

		return nvecs;



	event_irq = ioread32(&stdev->mmio_part_cfg->vep_vector_number);

	event_irq = ioread16(&stdev->mmio_part_cfg->vep_vector_number);

	if (event_irq < 0 || event_irq >= nvecs)

		return -EFAULT;
@@ -1324,16 +1491,16 @@ static void init_pff(struct switchtec_dev *stdev) 
	stdev->pff_csr_count = i;



	reg = ioread32(&pcfg->usp_pff_inst_id);

	if (reg < SWITCHTEC_MAX_PFF_CSR)

	if (reg < stdev->pff_csr_count)

		stdev->pff_local[reg] = 1;



	reg = ioread32(&pcfg->vep_pff_inst_id);

	if (reg < SWITCHTEC_MAX_PFF_CSR)

	if (reg < stdev->pff_csr_count)

		stdev->pff_local[reg] = 1;



	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {

		reg = ioread32(&pcfg->dsp_pff_inst_id[i]);

		if (reg < SWITCHTEC_MAX_PFF_CSR)

		if (reg < stdev->pff_csr_count)

			stdev->pff_local[reg] = 1;

	}

}
@@ -1344,12 +1511,13 @@ static int switchtec_init_pci(struct switchtec_dev *stdev, 
	int rc;

	void __iomem *map;

	unsigned long res_start, res_len;

	u32 __iomem *part_id;



	rc = pcim_enable_device(pdev);

	if (rc)

		return rc;



	rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));

	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));

	if (rc)

		return rc;
@@ -1378,7 +1546,15 @@ static int switchtec_init_pci(struct switchtec_dev *stdev, 
	stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;

	stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET;

	stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET;

	stdev->partition = ioread8(&stdev->mmio_sys_info->partition_id);



	if (stdev->gen == SWITCHTEC_GEN3)

		part_id = &stdev->mmio_sys_info->gen3.partition_id;

	else if (stdev->gen == SWITCHTEC_GEN4)

		part_id = &stdev->mmio_sys_info->gen4.partition_id;

	else

		return -ENOTSUPP;



	stdev->partition = ioread8(part_id);

	stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count);

	stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET;

	stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition];
@@ -1420,6 +1596,8 @@ static int switchtec_pci_probe(struct pci_dev *pdev, 
	if (IS_ERR(stdev))

		return PTR_ERR(stdev);



	stdev->gen = id->driver_data;



	rc = switchtec_init_pci(stdev, pdev);

	if (rc)

		goto err_put;
@@ -1467,7 +1645,7 @@ static void switchtec_pci_remove(struct pci_dev *pdev) 
	put_device(&stdev->dev);

}



#define SWITCHTEC_PCI_DEVICE(device_id) \

#define SWITCHTEC_PCI_DEVICE(device_id, gen) \

	{ \

		.vendor     = PCI_VENDOR_ID_MICROSEMI, \

		.device     = device_id, \
@@ -1475,6 +1653,7 @@ static void switchtec_pci_remove(struct pci_dev *pdev) 
		.subdevice  = PCI_ANY_ID, \

		.class      = (PCI_CLASS_MEMORY_OTHER << 8), \

		.class_mask = 0xFFFFFFFF, \

		.driver_data = gen, \

	}, \

	{ \

		.vendor     = PCI_VENDOR_ID_MICROSEMI, \
@@ -1483,39 +1662,58 @@ static void switchtec_pci_remove(struct pci_dev *pdev) 
		.subdevice  = PCI_ANY_ID, \

		.class      = (PCI_CLASS_BRIDGE_OTHER << 8), \

		.class_mask = 0xFFFFFFFF, \

		.driver_data = gen, \

	}



static const struct pci_device_id switchtec_pci_tbl[] = {

	SWITCHTEC_PCI_DEVICE(0x8531),  //PFX 24xG3

	SWITCHTEC_PCI_DEVICE(0x8532),  //PFX 32xG3

	SWITCHTEC_PCI_DEVICE(0x8533),  //PFX 48xG3

	SWITCHTEC_PCI_DEVICE(0x8534),  //PFX 64xG3

	SWITCHTEC_PCI_DEVICE(0x8535),  //PFX 80xG3

	SWITCHTEC_PCI_DEVICE(0x8536),  //PFX 96xG3

	SWITCHTEC_PCI_DEVICE(0x8541),  //PSX 24xG3

	SWITCHTEC_PCI_DEVICE(0x8542),  //PSX 32xG3

	SWITCHTEC_PCI_DEVICE(0x8543),  //PSX 48xG3

	SWITCHTEC_PCI_DEVICE(0x8544),  //PSX 64xG3

	SWITCHTEC_PCI_DEVICE(0x8545),  //PSX 80xG3

	SWITCHTEC_PCI_DEVICE(0x8546),  //PSX 96xG3

	SWITCHTEC_PCI_DEVICE(0x8551),  //PAX 24XG3

	SWITCHTEC_PCI_DEVICE(0x8552),  //PAX 32XG3

	SWITCHTEC_PCI_DEVICE(0x8553),  //PAX 48XG3

	SWITCHTEC_PCI_DEVICE(0x8554),  //PAX 64XG3

	SWITCHTEC_PCI_DEVICE(0x8555),  //PAX 80XG3

	SWITCHTEC_PCI_DEVICE(0x8556),  //PAX 96XG3

	SWITCHTEC_PCI_DEVICE(0x8561),  //PFXL 24XG3

	SWITCHTEC_PCI_DEVICE(0x8562),  //PFXL 32XG3

	SWITCHTEC_PCI_DEVICE(0x8563),  //PFXL 48XG3

	SWITCHTEC_PCI_DEVICE(0x8564),  //PFXL 64XG3

	SWITCHTEC_PCI_DEVICE(0x8565),  //PFXL 80XG3

	SWITCHTEC_PCI_DEVICE(0x8566),  //PFXL 96XG3

	SWITCHTEC_PCI_DEVICE(0x8571),  //PFXI 24XG3

	SWITCHTEC_PCI_DEVICE(0x8572),  //PFXI 32XG3

	SWITCHTEC_PCI_DEVICE(0x8573),  //PFXI 48XG3

	SWITCHTEC_PCI_DEVICE(0x8574),  //PFXI 64XG3

	SWITCHTEC_PCI_DEVICE(0x8575),  //PFXI 80XG3

	SWITCHTEC_PCI_DEVICE(0x8576),  //PFXI 96XG3

	SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3),  //PFX 24xG3

	SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3),  //PFX 32xG3

	SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3),  //PFX 48xG3

	SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3),  //PFX 64xG3

	SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3),  //PFX 80xG3

	SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3),  //PFX 96xG3

	SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3),  //PSX 24xG3

	SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3),  //PSX 32xG3

	SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3),  //PSX 48xG3

	SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3),  //PSX 64xG3

	SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3),  //PSX 80xG3

	SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3),  //PSX 96xG3

	SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3),  //PAX 24XG3

	SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3),  //PAX 32XG3

	SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3),  //PAX 48XG3

	SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3),  //PAX 64XG3

	SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3),  //PAX 80XG3

	SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3),  //PAX 96XG3

	SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3),  //PFXL 24XG3

	SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3),  //PFXL 32XG3

	SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3),  //PFXL 48XG3

	SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3),  //PFXL 64XG3

	SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3),  //PFXL 80XG3

	SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3),  //PFXL 96XG3

	SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3),  //PFXI 24XG3

	SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3),  //PFXI 32XG3

	SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3),  //PFXI 48XG3

	SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3),  //PFXI 64XG3

	SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3),  //PFXI 80XG3

	SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3),  //PFXI 96XG3

	SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4),  //PFX 100XG4

	SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4),  //PFX 84XG4

	SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4),  //PFX 68XG4

	SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4),  //PFX 52XG4

	SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4),  //PFX 36XG4

	SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4),  //PFX 28XG4

	SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4),  //PSX 100XG4

	SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4),  //PSX 84XG4

	SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4),  //PSX 68XG4

	SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4),  //PSX 52XG4

	SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4),  //PSX 36XG4

	SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4),  //PSX 28XG4

	SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4),  //PAX 100XG4

	SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4),  //PAX 84XG4

	SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4),  //PAX 68XG4

	SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4),  //PAX 52XG4

	SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4),  //PAX 36XG4

	SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4),  //PAX 28XG4

	{0}

};

MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl);

include/linux/switchtec.h

+141 −19

File changed.

Preview size limit exceeded, changes collapsed.

include/uapi/linux/switchtec_ioctl.h

+15 −2
Original line number Diff line number Diff line
@@ -32,7 +32,18 @@ 
#define SWITCHTEC_IOCTL_PART_VENDOR5	10

#define SWITCHTEC_IOCTL_PART_VENDOR6	11

#define SWITCHTEC_IOCTL_PART_VENDOR7	12

#define SWITCHTEC_IOCTL_NUM_PARTITIONS	13

#define SWITCHTEC_IOCTL_PART_BL2_0	13

#define SWITCHTEC_IOCTL_PART_BL2_1	14

#define SWITCHTEC_IOCTL_PART_MAP_0	15

#define SWITCHTEC_IOCTL_PART_MAP_1	16

#define SWITCHTEC_IOCTL_PART_KEY_0	17

#define SWITCHTEC_IOCTL_PART_KEY_1	18



#define SWITCHTEC_NUM_PARTITIONS_GEN3	13

#define SWITCHTEC_NUM_PARTITIONS_GEN4	19



/* obsolete: for compatibility with old userspace software */

#define SWITCHTEC_IOCTL_NUM_PARTITIONS	SWITCHTEC_NUM_PARTITIONS_GEN3



struct switchtec_ioctl_flash_info {

	__u64 flash_length;
@@ -98,7 +109,9 @@ struct switchtec_ioctl_event_summary { 
#define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT		27

#define SWITCHTEC_IOCTL_EVENT_LINK_STATE		28

#define SWITCHTEC_IOCTL_EVENT_GFMS			29

#define SWITCHTEC_IOCTL_MAX_EVENTS			30

#define SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY	30

#define SWITCHTEC_IOCTL_EVENT_UEC			31

#define SWITCHTEC_IOCTL_MAX_EVENTS			32



#define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1

#define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2