Commit 5270c7a2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.3-2' of...

Merge tag 'qcom-clk-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

Support for requesting the next power_off operation for a genpd to be
synchronous is introduced, and implemented in the GDSC driver. To allow
the GPU driver to request power_off to wait for the GDSC to actually
collapse.

Support for QDU1000/QRU1000 Global clock controller, SA8775P Global
clock controller, SM8550 TCSR and display clock controller, SM6350 clock
controller, nd MSM8996 CBF and APCS clock controllers is introduced.

Parent references are updated across a large number of clock drivers, to
align with the design changes since those drivers where introduced.
Similarly, test clocks has been dropped from a range of drivers.

A range of fixes for the MSM8996 CPU clock controller is introduced.

MSM8974 GCC is transitioned off the externally defined sleep_clk.

GDSC in the global clock controller for QCS404 is added, and various
parent definitions are cleaned up.

The SDCC core clocks on SM6115 are moved for floor_ops.

Programming of clk_dis_wait for GPU CX GDSC on SC7180 and SDM845 are
moved to use the recently introduced properties in the GDSC struct.

The RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock
is added on a variety of platforms.

The SMD RPM driver receives a big cleanup, in particular a move away
from duplicating declaration of identical clocks between multiple
platforms.
A few missing clocks across msm8998, msm8992, msm8916, qcs404 are added
as well.

Using devm_pm_runtime_enable() to clean up some duplication is done
across SM8250 display and video clock controllers, SM8450 display clock
controller and SC7280 LPASS clock controller.

Devicetree binding changes for above mentioned additions and changes are
introduced.

Support for postponing clk_disable_unused() until sync_state was
introduced, but later reverted again, awaiting an agreement on the
solution.

Lastly, a change to pad a few registers in the SM8250 DTS to 8 digits
was picked up in the wrong tree and kept here, to avoid rebasing.

* tag 'qcom-clk-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (142 commits)
  clk: qcom: Revert sync_state based clk_disable_unused
  dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml
  clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC
  clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC
  dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property
  clk: qcom: cpu-8996: add missing cputype include
  clk: qcom: gcc-sa8775p: remove unused variables
  clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform
  clk: qcom: add msm8996 Core Bus Framework (CBF) support
  dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller
  clk: qcom: add the driver for the MSM8996 APCS clocks
  clk: qcom: gcc-qcs404: fix duplicate initializer warning
  clk: qcom: cpu-8996: change setup sequence to follow vendor kernel
  clk: qcom: cpu-8996: fix PLL clock ops
  clk: qcom: cpu-8996: fix ACD initialization
  clk: qcom: cpu-8996: fix PLL configuration sequence
  clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call
  clk: qcom: cpu-8996: setup PLLs before registering clocks
  clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb
  clk: qcom: cpu-8996: skip ACD init if the setup is valid
  ...
parents 1b929c02 c1855dd0
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+18 −2
Original line number Diff line number Diff line
@@ -21,12 +21,16 @@ properties:

  clocks:
    items:
      - description: AHB
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: iface
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk

  '#clock-cells':
@@ -38,9 +42,18 @@ properties:
  '#power-domain-cells':
    const: 1

  power-domains:
    items:
      - description: MMCX power domain

  reg:
    maxItems: 1

  required-opps:
    maxItems: 1
    description:
      OPP node describing required MMCX performance point.

required:
  - compatible
  - reg
@@ -54,13 +67,16 @@ additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ad00000 {
      compatible = "qcom,sm8250-camcc";
      reg = <0x0ad00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
               <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
+44 −0
Original line number Diff line number Diff line
@@ -25,6 +25,30 @@ properties:
  compatible:
    const: qcom,gcc-apq8084

  clocks:
    items:
      - description: XO source
      - description: Sleep clock source
      - description: UFS RX symbol 0 clock
      - description: UFS RX symbol 1 clock
      - description: UFS TX symbol 0 clock
      - description: UFS TX symbol 1 clock
      - description: SATA ASIC0 clock
      - description: SATA RX clock
      - description: PCIe PIPE clock

  clock-names:
    items:
      - const: xo
      - const: sleep_clk
      - const: ufs_rx_symbol_0_clk_src
      - const: ufs_rx_symbol_1_clk_src
      - const: ufs_tx_symbol_0_clk_src
      - const: ufs_tx_symbol_1_clk_src
      - const: sata_asic0_clk
      - const: sata_rx_clk
      - const: pcie_pipe

required:
  - compatible

@@ -32,11 +56,31 @@ unevaluatedProperties: false

examples:
  - |
    /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
    clock-controller@fc400000 {
        compatible = "qcom,gcc-apq8084";
        reg = <0xfc400000 0x4000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;

        clocks = <&xo_board>,
                 <&sleep_clk>,
                 <&ufsphy 0>,
                 <&ufsphy 1>,
                 <&ufsphy 2>,
                 <&ufsphy 3>,
                 <&sata 0>,
                 <&sata 1>,
                 <&pcie_phy>;
        clock-names = "xo",
                      "sleep_clk",
                      "ufs_rx_symbol_0_clk_src",
                      "ufs_rx_symbol_1_clk_src",
                      "ufs_tx_symbol_0_clk_src",
                      "ufs_tx_symbol_1_clk_src",
                      "sata_asic0_clk",
                      "sata_rx_clk",
                      "pcie_pipe";
    };
...
+1 −5
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ properties:
      - description: Board XO source
      - description: Sleep clock source
      - description: Audio reference clock (Optional clock)
      - description: PLL test clock source (Optional clock)
    minItems: 2

  clock-names:
@@ -33,7 +32,6 @@ properties:
      - const: xo
      - const: sleep_clk
      - const: aud_ref_clk # Optional clock
      - const: core_bi_pll_test_se # Optional clock
    minItems: 2

required:
@@ -57,11 +55,9 @@ examples:
      reg = <0x00100000 0xb0000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&sleep>,
               <0>,
               <0>;
      clock-names = "xo",
                    "sleep_clk",
                    "aud_ref_clk",
                    "core_bi_pll_test_se";
                    "aud_ref_clk";
    };
...
+22 −16
Original line number Diff line number Diff line
@@ -20,26 +20,31 @@ properties:
  compatible:
    const: qcom,gcc-qcs404

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  reg:
    maxItems: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding.
  clocks:
    items:
      - description: XO source
      - description: Sleep clock source
      - description: PCIe 0 PIPE clock (optional)
      - description: DSI phy instance 0 dsi clock
      - description: DSI phy instance 0 byte clock
      - description: HDMI phy PLL clock

  clock-names:
    items:
      - const: cxo
      - const: sleep_clk
      - const: pcie_0_pipe_clk_src
      - const: dsi0pll
      - const: dsi0pllbyte
      - const: hdmi_pll

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false
allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
@@ -48,5 +53,6 @@ examples:
      reg = <0x01800000 0x80000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
+7 −0
Original line number Diff line number Diff line
@@ -55,6 +55,10 @@ properties:
      - description: First EMAC controller reference clock
      - description: Second EMAC controller reference clock

  power-domains:
    items:
      - description: CX domain

  protected-clocks:
    maxItems: 389

@@ -70,6 +74,8 @@ unevaluatedProperties: false
examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    clock-controller@100000 {
      compatible = "qcom,gcc-sc8280xp";
      reg = <0x00100000 0x1f0000>;
@@ -106,6 +112,7 @@ examples:
               <&pcie4_lane>,
               <&rxc0_ref_clk>,
               <&rxc1_ref_clk>;
      power-domains = <&rpmhpd SC8280XP_CX>;

      #clock-cells = <1>;
      #reset-cells = <1>;
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