Commit 523611f1 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-sdx55: get rid of test clock 



The test clock apparently it's not used by anyone upstream. Remove it.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-13-dmitry.baryshkov@linaro.org
parent e21f2a94

drivers/clk/qcom/gcc-sdx55.c

+0 −12
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 


enum {

	P_BI_TCXO,

	P_CORE_BI_PLL_TEST_SE,

	P_GPLL0_OUT_EVEN,

	P_GPLL0_OUT_MAIN,

	P_GPLL4_OUT_EVEN,
@@ -137,21 +136,18 @@ static const struct parent_map gcc_parent_map_0[] = { 
	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parents_0[] = {

	{ .fw_name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct clk_parent_data gcc_parents_0_ao[] = {

	{ .fw_name = "bi_tcxo_ao" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_2[] = {
@@ -160,7 +156,6 @@ static const struct parent_map gcc_parent_map_2[] = { 
	{ P_GPLL4_OUT_EVEN, 2 },

	{ P_GPLL5_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parents_2[] = {
@@ -169,7 +164,6 @@ static const struct clk_parent_data gcc_parents_2[] = { 
	{ .hw = &gpll4_out_even.clkr.hw },

	{ .hw = &gpll5.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_3[] = {
@@ -177,7 +171,6 @@ static const struct parent_map gcc_parent_map_3[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_SLEEP_CLK, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parents_3[] = {
@@ -185,19 +178,16 @@ static const struct clk_parent_data gcc_parents_3[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_4[] = {

	{ P_BI_TCXO, 0 },

	{ P_SLEEP_CLK, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parents_4[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "sleep_clk", .name = "sleep_clk" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_5[] = {
@@ -205,7 +195,6 @@ static const struct parent_map gcc_parent_map_5[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL4_OUT_EVEN, 2 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parents_5[] = {
@@ -213,7 +202,6 @@ static const struct clk_parent_data gcc_parents_5[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll4_out_even.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {