Commit 51ef6b00 authored by Amit Cohen's avatar Amit Cohen Committed by David S. Miller
Browse files

mlxsw: Use Switch Multicast ID Register Version 2 



The SMID-V2 register maps Multicast ID (MID) into a list of local ports.
It is a new version of SMID in order to support 1024 bits of local_port.

Add SMID-V2 register and use it instead of SMID.

Signed-off-by: default avatarAmit Cohen <amcohen@nvidia.com>
Reviewed-by: default avatarPetr Machata <petrm@nvidia.com>
Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e86ad8ce

drivers/net/ethernet/mellanox/mlxsw/reg.h

+47 −47
Original line number Diff line number Diff line
@@ -69,52 +69,6 @@ MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 
 */

MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);



/* SMID - Switch Multicast ID

 * --------------------------

 * The MID record maps from a MID (Multicast ID), which is a unique identifier

 * of the multicast group within the stacking domain, into a list of local

 * ports into which the packet is replicated.

 */

#define MLXSW_REG_SMID_ID 0x2007

#define MLXSW_REG_SMID_LEN 0x240



MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);



/* reg_smid_swid

 * Switch partition ID.

 * Access: Index

 */

MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);



/* reg_smid_mid

 * Multicast identifier - global identifier that represents the multicast group

 * across all devices.

 * Access: Index

 */

MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);



/* reg_smid_port

 * Local port memebership (1 bit per port).

 * Access: RW

 */

MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);



/* reg_smid_port_mask

 * Local port mask (1 bit per port).

 * Access: W

 */

MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);



static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,

				       u8 port, bool set)

{

	MLXSW_REG_ZERO(smid, payload);

	mlxsw_reg_smid_swid_set(payload, 0);

	mlxsw_reg_smid_mid_set(payload, mid);

	mlxsw_reg_smid_port_set(payload, port, set);

	mlxsw_reg_smid_port_mask_set(payload, port, 1);

}



/* SSPR - Switch System Port Record Register

 * -----------------------------------------

 * Configures the system port to local port mapping.
@@ -2105,6 +2059,52 @@ static inline void mlxsw_reg_sftr2_pack(char *payload, 
	mlxsw_reg_sftr2_port_mask_set(payload, port, 1);

}



/* SMID-V2 - Switch Multicast ID Version 2 Register

 * ------------------------------------------------

 * The MID record maps from a MID (Multicast ID), which is a unique identifier

 * of the multicast group within the stacking domain, into a list of local

 * ports into which the packet is replicated.

 */

#define MLXSW_REG_SMID2_ID 0x2034

#define MLXSW_REG_SMID2_LEN 0x120



MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);



/* reg_smid2_swid

 * Switch partition ID.

 * Access: Index

 */

MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);



/* reg_smid2_mid

 * Multicast identifier - global identifier that represents the multicast group

 * across all devices.

 * Access: Index

 */

MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);



/* reg_smid2_port

 * Local port memebership (1 bit per port).

 * Access: RW

 */

MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);



/* reg_smid2_port_mask

 * Local port mask (1 bit per port).

 * Access: WO

 */

MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);



static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,

					bool set)

{

	MLXSW_REG_ZERO(smid2, payload);

	mlxsw_reg_smid2_swid_set(payload, 0);

	mlxsw_reg_smid2_mid_set(payload, mid);

	mlxsw_reg_smid2_port_set(payload, port, set);

	mlxsw_reg_smid2_port_mask_set(payload, port, 1);

}



/* CWTP - Congetion WRED ECN TClass Profile

 * ----------------------------------------

 * Configures the profiles for queues of egress port and traffic class
@@ -12373,7 +12373,6 @@ static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 
static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {

	MLXSW_REG(sgcr),

	MLXSW_REG(spad),

	MLXSW_REG(smid),

	MLXSW_REG(sspr),

	MLXSW_REG(sfdat),

	MLXSW_REG(sfd),
@@ -12396,6 +12395,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(spvc),

	MLXSW_REG(spevet),

	MLXSW_REG(sftr2),

	MLXSW_REG(smid2),

	MLXSW_REG(cwtp),

	MLXSW_REG(cwtpm),

	MLXSW_REG(pgcr),

drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c

+25 −25
Original line number Diff line number Diff line
@@ -865,17 +865,17 @@ static int mlxsw_sp_port_mc_disabled_set(struct mlxsw_sp_port *mlxsw_sp_port, 
static int mlxsw_sp_smid_router_port_set(struct mlxsw_sp *mlxsw_sp,

					 u16 mid_idx, bool add)

{

	char *smid_pl;

	char *smid2_pl;

	int err;



	smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);

	if (!smid_pl)

	smid2_pl = kmalloc(MLXSW_REG_SMID2_LEN, GFP_KERNEL);

	if (!smid2_pl)

		return -ENOMEM;



	mlxsw_reg_smid_pack(smid_pl, mid_idx,

	mlxsw_reg_smid2_pack(smid2_pl, mid_idx,

			     mlxsw_sp_router_port(mlxsw_sp), add);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid), smid_pl);

	kfree(smid_pl);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);

	kfree(smid2_pl);

	return err;

}
@@ -1477,30 +1477,30 @@ static int mlxsw_sp_port_smid_full_entry(struct mlxsw_sp *mlxsw_sp, u16 mid_idx, 
					 long *ports_bitmap,

					 bool set_router_port)

{

	char *smid_pl;

	char *smid2_pl;

	int err, i;



	smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);

	if (!smid_pl)

	smid2_pl = kmalloc(MLXSW_REG_SMID2_LEN, GFP_KERNEL);

	if (!smid2_pl)

		return -ENOMEM;



	mlxsw_reg_smid_pack(smid_pl, mid_idx, 0, false);

	mlxsw_reg_smid2_pack(smid2_pl, mid_idx, 0, false);

	for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) {

		if (mlxsw_sp->ports[i])

			mlxsw_reg_smid_port_mask_set(smid_pl, i, 1);

			mlxsw_reg_smid2_port_mask_set(smid2_pl, i, 1);

	}



	mlxsw_reg_smid_port_mask_set(smid_pl,

	mlxsw_reg_smid2_port_mask_set(smid2_pl,

				      mlxsw_sp_router_port(mlxsw_sp), 1);



	for_each_set_bit(i, ports_bitmap, mlxsw_core_max_ports(mlxsw_sp->core))

		mlxsw_reg_smid_port_set(smid_pl, i, 1);

		mlxsw_reg_smid2_port_set(smid2_pl, i, 1);



	mlxsw_reg_smid_port_set(smid_pl, mlxsw_sp_router_port(mlxsw_sp),

	mlxsw_reg_smid2_port_set(smid2_pl, mlxsw_sp_router_port(mlxsw_sp),

				 set_router_port);



	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid), smid_pl);

	kfree(smid_pl);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);

	kfree(smid2_pl);

	return err;

}
@@ -1508,16 +1508,16 @@ static int mlxsw_sp_port_smid_set(struct mlxsw_sp_port *mlxsw_sp_port, 
				  u16 mid_idx, bool add)

{

	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;

	char *smid_pl;

	char *smid2_pl;

	int err;



	smid_pl = kmalloc(MLXSW_REG_SMID_LEN, GFP_KERNEL);

	if (!smid_pl)

	smid2_pl = kmalloc(MLXSW_REG_SMID2_LEN, GFP_KERNEL);

	if (!smid2_pl)

		return -ENOMEM;



	mlxsw_reg_smid_pack(smid_pl, mid_idx, mlxsw_sp_port->local_port, add);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid), smid_pl);

	kfree(smid_pl);

	mlxsw_reg_smid2_pack(smid2_pl, mid_idx, mlxsw_sp_port->local_port, add);

	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);

	kfree(smid2_pl);

	return err;

}