Commit 51eaa866 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ras_core_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 RAS updates from Borislav Petkov:

 - Fix the APEI MCE callback handler to consult the hardware about the
   granularity of the memory error instead of hard-coding it

 - Offline memory pages on Intel machines after 2 errors reported per
   page

* tag 'ras_core_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Retrieve poison range from hardware
  RAS/CEC: Reduce offline page threshold for Intel systems
parents 7db99f01 f9781bb1
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+12 −1
Original line number Diff line number Diff line
@@ -29,15 +29,26 @@
void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
{
	struct mce m;
	int lsb;

	if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
		return;

	/*
	 * Even if the ->validation_bits are set for address mask,
	 * to be extra safe, check and reject an error radius '0',
	 * and fall back to the default page size.
	 */
	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
		lsb = find_first_bit((void *)&mem_err->physical_addr_mask, PAGE_SHIFT);
	else
		lsb = PAGE_SHIFT;

	mce_setup(&m);
	m.bank = -1;
	/* Fake a memory read error with unknown channel */
	m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
	m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT;
	m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb;

	if (severity >= GHES_SEV_RECOVERABLE)
		m.status |= MCI_STATUS_UC;
+8 −0
Original line number Diff line number Diff line
@@ -556,6 +556,14 @@ static int __init cec_init(void)
	if (ce_arr.disabled)
		return -ENODEV;

	/*
	 * Intel systems may avoid uncorrectable errors
	 * if pages with corrected errors are aggressively
	 * taken offline.
	 */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		action_threshold = 2;

	ce_arr.array = (void *)get_zeroed_page(GFP_KERNEL);
	if (!ce_arr.array) {
		pr_err("Error allocating CE array page!\n");