Commit 51e39607 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
Browse files

MIPS: ralink: add memory definition for MT7620 



Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5183/
parent fe98f612

arch/mips/include/asm/mach-ralink/mt7620.h

+8 −0
Original line number Diff line number Diff line
@@ -50,6 +50,14 @@ 
#define SYSCFG0_DRAM_TYPE_DDR1		1

#define SYSCFG0_DRAM_TYPE_DDR2		2



#define MT7620_DRAM_BASE		0x0

#define MT7620_SDRAM_SIZE_MIN		2

#define MT7620_SDRAM_SIZE_MAX		64

#define MT7620_DDR1_SIZE_MIN		32

#define MT7620_DDR1_SIZE_MAX		128

#define MT7620_DDR2_SIZE_MIN		32

#define MT7620_DDR2_SIZE_MAX		256



#define MT7620_GPIO_MODE_I2C		BIT(0)

#define MT7620_GPIO_MODE_UART0_SHIFT	2

#define MT7620_GPIO_MODE_UART0_MASK	0x7

arch/mips/ralink/mt7620.c

+20 −0
Original line number Diff line number Diff line
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info) 


	cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);

	dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;



	switch (dram_type) {

	case SYSCFG0_DRAM_TYPE_SDRAM:

		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;

		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;

		break;



	case SYSCFG0_DRAM_TYPE_DDR1:

		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;

		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;

		break;



	case SYSCFG0_DRAM_TYPE_DDR2:

		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;

		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;

		break;

	default:

		BUG();

	}

	soc_info->mem_base = MT7620_DRAM_BASE;

}