Commit 51dfc614 authored by Fred's avatar Fred Committed by Ulf Hansson
Browse files

mmc: sdhci-pci-o2micro: Fix SDR50 mode timing issue 



Change SDR50 mode clock source from DLL output clock to PLL open clock
1.HS200 and SDR104 mode select DLL output clock
2.SDR50 mode select PLL open clock

Signed-off-by: default avatarFred <fred.ai@bayhubtech.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230223120450.16858-1-fredaibayhubtech@126.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent ca6b5fe2

drivers/mmc/host/sdhci-pci-o2micro.c

+16 −14
Original line number Diff line number Diff line
@@ -339,6 +339,8 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 
	reg_val &= ~SDHCI_CLOCK_CARD_EN;

	sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);



	if ((host->timing == MMC_TIMING_MMC_HS200) ||

		(host->timing == MMC_TIMING_UHS_SDR104)) {

		/* UnLock WP */

		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);

		scratch_8 &= 0x7f;
@@ -354,7 +356,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) 
		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);

		scratch_8 |= 0x80;

		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);



	}

	/* Start clk */

	reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

	reg_val |= SDHCI_CLOCK_CARD_EN;