Commit 51b072de authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/gmbus: split out gmbus regs in a separate file 



Declutter i915_reg.h, and also observe very few places need the gmbus
register defitions.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/820807f404e548ab365b934d44f01b306eaa28c2.1661855191.git.jani.nikula@intel.com
parent fe28c7c1

drivers/gpu/drm/i915/display/intel_gmbus.c

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include "intel_de.h"

#include "intel_display_types.h"

#include "intel_gmbus.h"

#include "intel_gmbus_regs.h"



struct intel_gmbus {

	struct i2c_adapter adapter;

drivers/gpu/drm/i915/display/intel_gmbus_regs.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2022 Intel Corporation

 */



#ifndef __INTEL_GMBUS_REGS_H__

#define __INTEL_GMBUS_REGS_H__



#include "i915_reg_defs.h"



#define GPIO(gpio)		_MMIO(dev_priv->display.gmbus.mmio_base + 0x5010 + \

				      4 * (gpio))



# define GPIO_CLOCK_DIR_MASK		(1 << 0)

# define GPIO_CLOCK_DIR_IN		(0 << 1)

# define GPIO_CLOCK_DIR_OUT		(1 << 1)

# define GPIO_CLOCK_VAL_MASK		(1 << 2)

# define GPIO_CLOCK_VAL_OUT		(1 << 3)

# define GPIO_CLOCK_VAL_IN		(1 << 4)

# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)

# define GPIO_DATA_DIR_MASK		(1 << 8)

# define GPIO_DATA_DIR_IN		(0 << 9)

# define GPIO_DATA_DIR_OUT		(1 << 9)

# define GPIO_DATA_VAL_MASK		(1 << 10)

# define GPIO_DATA_VAL_OUT		(1 << 11)

# define GPIO_DATA_VAL_IN		(1 << 12)

# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)



#define GMBUS0			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */

#define   GMBUS_AKSV_SELECT	(1 << 11)

#define   GMBUS_RATE_100KHZ	(0 << 8)

#define   GMBUS_RATE_50KHZ	(1 << 8)

#define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */

#define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */

#define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */

#define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)



#define GMBUS1			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */

#define   GMBUS_SW_CLR_INT	(1 << 31)

#define   GMBUS_SW_RDY		(1 << 30)

#define   GMBUS_ENT		(1 << 29) /* enable timeout */

#define   GMBUS_CYCLE_NONE	(0 << 25)

#define   GMBUS_CYCLE_WAIT	(1 << 25)

#define   GMBUS_CYCLE_INDEX	(2 << 25)

#define   GMBUS_CYCLE_STOP	(4 << 25)

#define   GMBUS_BYTE_COUNT_SHIFT 16

#define   GMBUS_BYTE_COUNT_MAX   256U

#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U

#define   GMBUS_SLAVE_INDEX_SHIFT 8

#define   GMBUS_SLAVE_ADDR_SHIFT 1

#define   GMBUS_SLAVE_READ	(1 << 0)

#define   GMBUS_SLAVE_WRITE	(0 << 0)

#define GMBUS2			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5108) /* status */

#define   GMBUS_INUSE		(1 << 15)

#define   GMBUS_HW_WAIT_PHASE	(1 << 14)

#define   GMBUS_STALL_TIMEOUT	(1 << 13)

#define   GMBUS_INT		(1 << 12)

#define   GMBUS_HW_RDY		(1 << 11)

#define   GMBUS_SATOER		(1 << 10)

#define   GMBUS_ACTIVE		(1 << 9)

#define GMBUS3			_MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */

#define GMBUS4			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */

#define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)

#define   GMBUS_NAK_EN		(1 << 3)

#define   GMBUS_IDLE_EN		(1 << 2)

#define   GMBUS_HW_WAIT_EN	(1 << 1)

#define   GMBUS_HW_RDY_EN	(1 << 0)

#define GMBUS5			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5120) /* byte index */

#define   GMBUS_2BYTE_INDEX_EN	(1 << 31)



#endif /* __INTEL_GMBUS_REGS_H__ */

drivers/gpu/drm/i915/gvt/edid.c

+2 −1
Original line number Diff line number Diff line
@@ -32,9 +32,10 @@ 
 *

 */



#include "display/intel_gmbus_regs.h"

#include "gvt.h"

#include "i915_drv.h"

#include "i915_reg.h"

#include "gvt.h"



#define GMBUS1_TOTAL_BYTES_SHIFT 16

#define GMBUS1_TOTAL_BYTES_MASK 0x1ff

drivers/gpu/drm/i915/i915_reg.h

+0 −63
Original line number Diff line number Diff line
@@ -1461,69 +1461,6 @@ 
#define   FBC_REND_NUKE			REG_BIT(2)

#define   FBC_REND_CACHE_CLEAN		REG_BIT(1)



/*

 * GPIO regs

 */

#define GPIO(gpio)		_MMIO(dev_priv->display.gmbus.mmio_base + 0x5010 + \

				      4 * (gpio))



# define GPIO_CLOCK_DIR_MASK		(1 << 0)

# define GPIO_CLOCK_DIR_IN		(0 << 1)

# define GPIO_CLOCK_DIR_OUT		(1 << 1)

# define GPIO_CLOCK_VAL_MASK		(1 << 2)

# define GPIO_CLOCK_VAL_OUT		(1 << 3)

# define GPIO_CLOCK_VAL_IN		(1 << 4)

# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)

# define GPIO_DATA_DIR_MASK		(1 << 8)

# define GPIO_DATA_DIR_IN		(0 << 9)

# define GPIO_DATA_DIR_OUT		(1 << 9)

# define GPIO_DATA_VAL_MASK		(1 << 10)

# define GPIO_DATA_VAL_OUT		(1 << 11)

# define GPIO_DATA_VAL_IN		(1 << 12)

# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)



#define GMBUS0			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */

#define   GMBUS_AKSV_SELECT	(1 << 11)

#define   GMBUS_RATE_100KHZ	(0 << 8)

#define   GMBUS_RATE_50KHZ	(1 << 8)

#define   GMBUS_RATE_400KHZ	(2 << 8) /* reserved on Pineview */

#define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */

#define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */

#define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)



#define GMBUS1			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */

#define   GMBUS_SW_CLR_INT	(1 << 31)

#define   GMBUS_SW_RDY		(1 << 30)

#define   GMBUS_ENT		(1 << 29) /* enable timeout */

#define   GMBUS_CYCLE_NONE	(0 << 25)

#define   GMBUS_CYCLE_WAIT	(1 << 25)

#define   GMBUS_CYCLE_INDEX	(2 << 25)

#define   GMBUS_CYCLE_STOP	(4 << 25)

#define   GMBUS_BYTE_COUNT_SHIFT 16

#define   GMBUS_BYTE_COUNT_MAX   256U

#define   GEN9_GMBUS_BYTE_COUNT_MAX 511U

#define   GMBUS_SLAVE_INDEX_SHIFT 8

#define   GMBUS_SLAVE_ADDR_SHIFT 1

#define   GMBUS_SLAVE_READ	(1 << 0)

#define   GMBUS_SLAVE_WRITE	(0 << 0)

#define GMBUS2			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5108) /* status */

#define   GMBUS_INUSE		(1 << 15)

#define   GMBUS_HW_WAIT_PHASE	(1 << 14)

#define   GMBUS_STALL_TIMEOUT	(1 << 13)

#define   GMBUS_INT		(1 << 12)

#define   GMBUS_HW_RDY		(1 << 11)

#define   GMBUS_SATOER		(1 << 10)

#define   GMBUS_ACTIVE		(1 << 9)

#define GMBUS3			_MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */

#define GMBUS4			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */

#define   GMBUS_SLAVE_TIMEOUT_EN (1 << 4)

#define   GMBUS_NAK_EN		(1 << 3)

#define   GMBUS_IDLE_EN		(1 << 2)

#define   GMBUS_HW_WAIT_EN	(1 << 1)

#define   GMBUS_HW_RDY_EN	(1 << 0)

#define GMBUS5			_MMIO(dev_priv->display.gmbus.mmio_base + 0x5120) /* byte index */

#define   GMBUS_2BYTE_INDEX_EN	(1 << 31)



/*

 * Clock control & power management

 */