Commit 5188049c authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: Add base SM8450 DTSI 



This add based DTSI for SM8450 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interuupt-controller which helps to boot to
shell with console on boards with this SoC

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215043440.605624-2-vkoul@kernel.org
parent 72cb4c48

arch/arm64/boot/dts/qcom/sm8450.dtsi

0 → 100644
+476 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause

/*

 * Copyright (c) 2021, Linaro Limited

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-sm8450.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>



/ {

	interrupt-parent = <&intc>;



	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <76800000>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32000>;

		};

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			power-domains = <&CPU_PD0>;

			power-domain-names = "psci";

			L2_0: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				      compatible = "cache";

				};

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			power-domains = <&CPU_PD1>;

			power-domain-names = "psci";

			L2_100: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			power-domains = <&CPU_PD2>;

			power-domain-names = "psci";

			L2_200: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			power-domains = <&CPU_PD3>;

			power-domain-names = "psci";

			L2_300: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			power-domains = <&CPU_PD4>;

			power-domain-names = "psci";

			L2_400: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			power-domains = <&CPU_PD5>;

			power-domain-names = "psci";

			L2_500: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};



		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			power-domains = <&CPU_PD6>;

			power-domain-names = "psci";

			L2_600: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo780";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			power-domains = <&CPU_PD7>;

			power-domain-names = "psci";

			L2_700: l2-cache {

			      compatible = "cache";

			      next-level-cache = <&L3_0>;

			};

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&CPU0>;

				};



				core1 {

					cpu = <&CPU1>;

				};



				core2 {

					cpu = <&CPU2>;

				};



				core3 {

					cpu = <&CPU3>;

				};



				core4 {

					cpu = <&CPU4>;

				};



				core5 {

					cpu = <&CPU5>;

				};



				core6 {

					cpu = <&CPU6>;

				};



				core7 {

					cpu = <&CPU7>;

				};

			};

		};



		idle-states {

			entry-method = "psci";



			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {

				compatible = "arm,idle-state";

				idle-state-name = "silver-rail-power-collapse";

				arm,psci-suspend-param = <0x40000004>;

				entry-latency-us = <274>;

				exit-latency-us = <480>;

				min-residency-us = <3934>;

				local-timer-stop;

			};



			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {

				compatible = "arm,idle-state";

				idle-state-name = "gold-rail-power-collapse";

				arm,psci-suspend-param = <0x40000004>;

				entry-latency-us = <327>;

				exit-latency-us = <1502>;

				min-residency-us = <4488>;

				local-timer-stop;

			};

		};



		domain-idle-states {

			CLUSTER_SLEEP_0: cluster-sleep-0 {

				compatible = "domain-idle-state";

				idle-state-name = "cluster-l3-off";

				arm,psci-suspend-param = <0x4100c344>;

				entry-latency-us = <584>;

				exit-latency-us = <2332>;

				min-residency-us = <6118>;

				local-timer-stop;

			};



			CLUSTER_SLEEP_1: cluster-sleep-1 {

				compatible = "domain-idle-state";

				idle-state-name = "cluster-power-collapse";

				arm,psci-suspend-param = <0x4100c344>;

				entry-latency-us = <2893>;

				exit-latency-us = <4023>;

				min-residency-us = <9987>;

				local-timer-stop;

			};

		};

	};



	firmware {

		scm: scm {

			compatible = "qcom,scm-sm8450", "qcom,scm";

			#reset-cells = <1>;

		};

	};



	memory@a0000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0x0 0xa0000000 0x0 0x0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";



		CPU_PD0: cpu0 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD1: cpu1 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD2: cpu2 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD3: cpu3 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;

		};



		CPU_PD4: cpu4 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD5: cpu5 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD6: cpu6 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CPU_PD7: cpu7 {

			#power-domain-cells = <0>;

			power-domains = <&CLUSTER_PD>;

			domain-idle-states = <&BIG_CPU_SLEEP_0>;

		};



		CLUSTER_PD: cpu-cluster0 {

			#power-domain-cells = <0>;

			domain-idle-states = <&CLUSTER_SLEEP_0>;

		};

	};



	soc: soc@0 {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0 0 0 0 0x10 0>;

		dma-ranges = <0 0 0 0 0x10 0>;

		compatible = "simple-bus";



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sm8450";

			reg = <0x0 0x00100000 0x0 0x1f4200>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

			clock-names = "bi_tcxo", "sleep_clk";

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;

		};



		qupv3_id_0: geniqup@9c0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x009c0000 0x0 0x2000>;

			clock-names = "m-ahb", "s-ahb";

			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			status = "disabled";



			uart7: serial@99c000 {

				compatible = "qcom,geni-debug-uart";

				reg = <0 0x0099c000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;

				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0x0 0x01f40000 0x0 0x40000>;

			#hwlock-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8450-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;

			qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,

					  <94 609 31>, <125 63 1>, <126 716 12>;

			#interrupt-cells = <2>;

			interrupt-parent = <&intc>;

			interrupt-controller;

		};



		intc: interrupt-controller@17100000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;

			interrupt-controller;

			#redistributor-regions = <1>;

			redistributor-stride = <0x0 0x40000>;

			reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */

			      <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		timer@17420000 {

			compatible = "arm,armv7-timer-mem";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			reg = <0x0 0x17420000 0x0 0x1000>;

			clock-frequency = <19200000>;



			frame@17421000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17421000 0x0 0x1000>,

				      <0x0 0x17422000 0x0 0x1000>;

			};



			frame@17423000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17423000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17425000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17425000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17427000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17427000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17429000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17429000 0x0 0x1000>;

				status = "disabled";

			};



			frame@1742b000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x1742b000 0x0 0x1000>;

				status = "disabled";

			};



			frame@1742d000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x1742d000 0x0 0x1000>;

				status = "disabled";

			};

		};



		apps_rsc: rsc@17a00000 {

			label = "apps_rsc";

			compatible = "qcom,rpmh-rsc";

			reg = <0x0 0x17a00000 0x0 0x10000>,

			      <0x0 0x17a10000 0x0 0x10000>,

			      <0x0 0x17a20000 0x0 0x10000>,

			      <0x0 0x17a30000 0x0 0x10000>;

			reg-names = "drv-0", "drv-1", "drv-2", "drv-3";

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

			qcom,tcs-offset = <0xd00>;

			qcom,drv-id = <2>;

			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,

					  <WAKE_TCS    2>, <CONTROL_TCS 0>;



			apps_bcm_voter: bcm-voter {

				compatible = "qcom,bcm-voter";

			};



			rpmhcc: clock-controller {

				compatible = "qcom,sm8450-rpmh-clk";

				#clock-cells = <1>;

				clock-names = "xo";

				clocks = <&xo_board>;

			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <19200000>;

	};

};