Commit 514946d1 authored by Maxim Levitsky's avatar Maxim Levitsky Committed by Paolo Bonzini
Browse files

KVM: x86: VMX: __kvm_apic_update_irr must update the IRR atomically 



If APICv is inhibited, then IPIs from peer vCPUs are done by
atomically setting bits in IRR.

This means, that when __kvm_apic_update_irr copies PIR to IRR,
it has to modify IRR atomically as well.

Signed-off-by: default avatarMaxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20230726135945.260841-2-mlevitsk@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 6eaae198

arch/x86/kvm/lapic.c

+13 −7
Original line number Diff line number Diff line
@@ -637,16 +637,22 @@ bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) 
	*max_irr = -1;



	for (i = vec = 0; i <= 7; i++, vec += 32) {

		u32 *p_irr = (u32 *)(regs + APIC_IRR + i * 0x10);



		irr_val = *p_irr;

		pir_val = READ_ONCE(pir[i]);

		irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));



		if (pir_val) {

			pir_val = xchg(&pir[i], 0);



			prev_irr_val = irr_val;

			irr_val |= xchg(&pir[i], 0);

			*((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;

			if (prev_irr_val != irr_val) {

				max_updated_irr =

					__fls(irr_val ^ prev_irr_val) + vec;

			}

			do {

				irr_val = prev_irr_val | pir_val;

			} while (prev_irr_val != irr_val &&

				 !try_cmpxchg(p_irr, &prev_irr_val, irr_val));



			if (prev_irr_val != irr_val)

				max_updated_irr = __fls(irr_val ^ prev_irr_val) + vec;

		}

		if (irr_val)

			*max_irr = __fls(irr_val) + vec;