Commit 50d602d8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull mailbox updates from Jassi Brar:
 "qcom:
   - add support for MSM8976

  mtk:
   - enable mt8186
   - add ADSP controller driver

  ti:
   - use poll mode during suspend

  tegra:
   - fix tx channel flush

  imx:
   - add i.MX8 SECO MU support
   - prepare for, and add iMX93 support"

* tag 'mailbox-v5.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  dt-bindings: mailbox: add definition for mt8186
  mailbox: ti-msgmgr: Operate mailbox in polled mode during system suspend
  mailbox: ti-msgmgr: Refactor message read during interrupt handler
  mailbox: imx: support i.MX93 S401 MU
  mailbox: imx: support dual interrupts
  mailbox: imx: extend irq to an array
  dt-bindings: mailbox: imx-mu: add i.MX93 S4 MU support
  dt-bindings: mailbox: imx-mu: add i.MX93 MU
  mailbox: imx: add i.MX8 SECO MU support
  mailbox: imx: introduce rxdb callback
  dt-bindings: mailbox: imx-mu: add i.MX8 SECO MU support
  mailbox: imx: enlarge timeout while reading/writing messages to SCFW
  mailbox: imx: fix crash in resume on i.mx8ulp
  mailbox: imx: fix wakeup failure from freeze mode
  mailbox: mediatek: add support for adsp mailbox controller
  dt-bindings: mailbox: mtk,adsp-mbox: add mtk adsp-mbox document
  mailbox: qcom-apcs-ipc: Add compatible for MSM8976 SoC
  dt-bindings: mailbox: Add compatible for the MSM8976
  mailbox: tegra-hsp: Flush whole channel
parents dfb0a0b7 1b0d0f7c
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+34 −1
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@@ -28,7 +28,12 @@ properties:
      - const: fsl,imx7ulp-mu
      - const: fsl,imx8ulp-mu
      - const: fsl,imx8-mu-scu
      - const: fsl,imx8-mu-seco
      - const: fsl,imx93-mu-s4
      - const: fsl,imx8ulp-mu-s4
      - items:
          - const: fsl,imx93-mu
          - const: fsl,imx8ulp-mu
      - items:
          - enum:
              - fsl,imx7s-mu
@@ -51,7 +56,14 @@ properties:
    maxItems: 1

  interrupts:
    maxItems: 1
    minItems: 1
    maxItems: 2

  interrupt-names:
    minItems: 1
    items:
      - const: tx
      - const: rx

  "#mbox-cells":
    description: |
@@ -86,6 +98,27 @@ required:
  - interrupts
  - "#mbox-cells"

allOf:
  - if:
      properties:
        compatible:
          enum:
            - fsl,imx93-mu-s4
    then:
      properties:
        interrupt-names:
          minItems: 2
        interrupts:
          minItems: 2

    else:
      properties:
        interrupts:
          maxItems: 1
      not:
        required:
          - interrupt-names

additionalProperties: false

examples:
+50 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek ADSP mailbox

maintainers:
  - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>

description: |
  The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
  to ommunicate with ADSP by passing messages through two mailbox channels.
  The MTK ADSP mailbox IPC also provides the ability for one processor to
  signal the other processor using interrupts.

properties:
  compatible:
    items:
      - const: mediatek,mt8195-adsp-mbox

  "#mbox-cells":
    const: 0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - "#mbox-cells"
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    adsp_mailbox0:mailbox@10816000 {
        compatible = "mediatek,mt8195-adsp-mbox";
        #mbox-cells = <0>;
        reg = <0x10816000 0x1000>;
        interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
    };
+5 −3
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@@ -10,7 +10,8 @@ mailbox.txt for generic information about mailbox device-tree bindings.

Required properties:
- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce",
  "mediatek,mt8192-gce", "mediatek,mt8195-gce" or "mediatek,mt6779-gce".
  "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or
  "mediatek,mt6779-gce".
- reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding
@@ -40,8 +41,9 @@ Optional properties for a client mutex node:
  defined in 'dt-bindings/gce/<chip>-gce.h'.

Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8192-gce.h',
'dt-bindings/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'.
'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8186-gce.h'
'dt-bindings/gce/mt8192-gce.h', 'dt-bindings/gce/mt8195-gce.h' or
'dt-bindings/gce/mt6779-gce.h'.
Such as sub-system ids, thread priority, event ids.

Example:
+1 −0
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@@ -21,6 +21,7 @@ properties:
      - qcom,msm8916-apcs-kpss-global
      - qcom,msm8939-apcs-kpss-global
      - qcom,msm8953-apcs-kpss-global
      - qcom,msm8976-apcs-kpss-global
      - qcom,msm8994-apcs-kpss-global
      - qcom,msm8996-apcs-hmss-global
      - qcom,msm8998-apcs-hmss-global
+9 −0
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@@ -238,6 +238,15 @@ config STM32_IPCC
	  with hardware for Inter-Processor Communication Controller (IPCC)
	  between processors. Say Y here if you want to have this support.

config MTK_ADSP_MBOX
	tristate "MediaTek ADSP Mailbox Controller"
	depends on ARCH_MEDIATEK || COMPILE_TEST
	help
          Say yes here to add support for "MediaTek ADSP Mailbox Controller.
          This mailbox driver is used to send notification or short message
          between processors with ADSP. It will place the message to share
	  buffer and will access the ipc control.

config MTK_CMDQ_MBOX
	tristate "MediaTek CMDQ Mailbox Support"
	depends on ARCH_MEDIATEK || COMPILE_TEST
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